Hi,
On 28.07.21 14:47, Renaud Barbier wrote:
> Set the NAND timings and enable the IFC NAND driver.
>
> Signed-off-by: Renaud Barbier <renaud.barbier@xxxxxxxxx>
> ---
> arch/arm/boards/ls1046ardb/board.c | 26 ++++++++++++++++++++++++++
> arch/arm/configs/layerscape_defconfig | 12 ++++++++++++
> 2 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c
> index ef68e9c7f9..5573d5b486 100644
> --- a/arch/arm/boards/ls1046ardb/board.c
> +++ b/arch/arm/boards/ls1046ardb/board.c
> @@ -12,6 +12,7 @@
> #include <linux/sizes.h>
> #include <linux/clk.h>
> #include <linux/clkdev.h>
> +#include <linux/fsl_ifc.h>
> #include <asm/system.h>
> #include <mach/layerscape.h>
> #include <mach/bbu.h>
> @@ -147,6 +148,31 @@ static int rdb_mem_init(void)
> }
> mem_initcall(rdb_mem_init);
>
> +static int rdb_nand_init(void)
> +{
You should check against board compatible here.
> + /* NAND mapping and timings. Only for Linux use. */
Why is this only for Linux use? You use the driver in barebox, don't you?
> + set_ifc_cspr(IFC_CS0, CSPR_PHYS_ADDR(0x7e800000) | CSPR_PORT_SIZE_8 |
> + CSPR_MSEL_NAND | CSPR_V);
> + set_ifc_csor(IFC_CS0, CSOR_NAND_ECC_ENC_EN | CSOR_NAND_ECC_DEC_EN |
> + CSOR_NAND_ECC_MODE_8 |
> + CSOR_NAND_RAL_3 | CSOR_NAND_PGS_4K |
> + CSOR_NAND_SPRZ_224 | CSOR_NAND_PB(64) |
> + CSOR_NAND_TRHZ_20);
> + set_ifc_amask(IFC_CS0, IFC_AMASK(64*1024));
> + set_ifc_ftim(IFC_CS0, IFC_FTIM0, FTIM0_NAND_TCCST(0x07) |
> + FTIM0_NAND_TWP(0x18) | FTIM0_NAND_TWCHT(0x07) |
> + FTIM0_NAND_TWH(0x0a));
> + set_ifc_ftim(IFC_CS0, IFC_FTIM1, FTIM1_NAND_TADLE(0x32) |
> + FTIM1_NAND_TWBE(0x39) | FTIM1_NAND_TRR(0x0e)|
> + FTIM1_NAND_TRP(0x18));
> + set_ifc_ftim(IFC_CS0, IFC_FTIM2, FTIM2_NAND_TRAD(0xf) |
> + FTIM2_NAND_TREH(0xa) | FTIM2_NAND_TWHRE(0x1e));
> + set_ifc_ftim(IFC_CS0, IFC_FTIM3, 0);
I assume there are no DT bindings describing these parameters for the
IFC driver to consume?
> +
> + return 0;
> +}
> +core_initcall(rdb_nand_init);
Cheers,
Ahmad
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