On Sat, Jun 19, 2021 at 06:50:26AM +0200, Ahmad Fatoum wrote: > The changes allow barebox to run second stage (after ddrinit and second > boot) on the BeagleV beta board. It does everything necessary to support > Ethernet, MMC, GPIO, pinmux, pinconf, clock, reset, watchdog, HWRNG and > DMA between CPU and the cache-incoherent DMA masters. > > The current vendor kernel doesn't care much for low-level > initialization, depending on pinmux, pinconf, clock and reset to happen > completely in the bootloader. This makes an initial bootloader port > much more complex, because you need not only care about the peripherals > you use yourself, but those that Linux may want to access to. > > For this reason, there is a starfive-pwrseq driver that binds against > some nodes like the neural network accelerator, which we will probably > never support, but at least tickles it resets and enables its clocks. > > Some peripherals require writing magic values into registers, which > this series doesn't do. If your boot hangs, consider checking out: > > https://github.com/a3f/barebox/tree/beaglev > > instead, which imports some vendor boot code to support more > peripherals. This series is sufficient to have barebox boot kernels that > do their own initialization though. Problem is there are no such kernels > yet ^^. > > Candidates for further steps: > > - Support more peripherals in starfive-pwrseq > - Get Designware i2c controller working, so we can use PMIC for reset > - Get Cadence QSPI working, so barebox can flash itself and use > environment on flash > - Figure out the ticket lottery stuff, so we can boot multi-core > - Replace ddrinit and secondboot with PBL, load from there opensbi > and then return to barebox proper > - Complete missing clock tree info when Documentation is available > > I can use a hand impementing these, so patches are most certainly > welcome (Antony, I am looking at you ;-). > > v1 was here: > https://lore.barebox.org/barebox/20210531073821.15257-1-a.fatoum@xxxxxxxxxxxxxx/ > > v1 -> v2: > - Dropped untested PMIC and flash chip commits. i2c and qspi controller > drivers in tree don't yet work for BeagleV > - remove clocksource clutter from console > - import S-/M-Mode multi-image series, so we can build all images for > the same ISA in one go > - Drop barebox,provide-mac-address from OTP driver. This is now done > via nvmem-cells reference > - Replace coherent memory from SRAM allocator with non-1:1 mapping: > Give devices the cached <= 32 bit address, as they are > cache-incoherent anyway, and use the > 32 bit uncached address from > CPU side. Works beautifully > - Drop 64-bit-conversion for dw_mmc. Sascha did it for rk3568 and it > works for BeagleV too > - Check Designware ETH coherent memory allocation against mask > - Rebase on newest clock changes > - Disable clocks after resets (Sascha) > - Move repsonsibility of keeping reset-synchronous clocks needed > for normal operation enabled to drivers (Sascha, off-list) > - Handle fence.i trap in exception handler to support SoCs without > Zifencei ISA extension > - Add some static clock initialization to starfive-pwrseq driver > - Add pinctrl driver support > - Add GPIO driver support > - Add board support > > > Ahmad Fatoum (29): > clocksource: RISC-V: demote probe success messages to debug level > RISC-V: virt: select only one timer > RISC-V: extend multi-image to support both S- and M-Mode > RISC-V: cpuinfo: return some output for non-SBI systems as well > RISC-V: S-Mode: propagate Hart ID > RISC-V: erizo: make it easier to reuse ns16550 debug_ll > RISC-V: socs: add Kconfig entry for StarFive JH7100 > nvmem: add StarFive OTP support > RISC-V: dma: support multiple dma_alloc_coherent backends > RISC-V: add exception support > RISC-V: support incoherent I-Cache > drivers: soc: sifive: add basic L2 cache controller driver > soc: starfive: add support for JH7100 incoherent interconnect > soc: sifive: l2_cache: enable maximum available cache ways > net: designware: fix non-1:1 mapped 64-bit systems > net: designware: add support for IP integrated into StarFive SoC > mci: allocate DMA-able memory > mci: allocate sector_buf on demand > dma: allocate 32-byte aligned buffers by default > mci: dw_mmc: add optional reset line > mci: dw_mmc: match against StarFive MMC compatibles > clk: add initial StarFive clock support > reset: add StarFive reset controller driver > watchdog: add StarFive watchdog driver > hw_random: add driver for RNG on StarFive SoC > reset: add device_reset_all helper > gpio: add support for StarFive GPIO controller > misc: add power sequencing driver for initializing StarFive > peripherals > RISC-V: StarFive: add board support for BeagleV Starlight Applied, thanks Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
