Previous boot stages may not enable all cache ways, e.g. because they
are running from L2 cache. By the time barebox proper is running,
execution should be from main SDRAM, so it's ok now to enable the
maximum available count of cache ways.
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
drivers/soc/sifive/sifive_l2_cache.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 9e54474f7ae8..a1e9a1062204 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -15,6 +15,7 @@
#include <init.h>
#include <soc/sifive/l2_cache.h>
#include <asm/barrier.h>
+#include <linux/bitops.h>
#define SIFIVE_L2_DIRECCFIX_LOW 0x100
#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
@@ -40,6 +41,9 @@
#define SIFIVE_L2_MAX_ECCINTR 4
+#define MASK_NUM_WAYS GENMASK(15, 8)
+#define NUM_WAYS_SHIFT 8
+
#define SIFIVE_L2_FLUSH64_LINE_LEN 64
static void __iomem *l2_base = NULL;
@@ -84,6 +88,19 @@ void sifive_l2_flush64_range(dma_addr_t start, dma_addr_t end)
}
}
+static void sifive_l2_enable_ways(void)
+{
+ u32 config;
+ u32 ways;
+
+ config = readl(l2_base + SIFIVE_L2_CONFIG);
+ ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+ mb();
+ writel(ways - 1, l2_base + SIFIVE_L2_WAYENABLE);
+ mb();
+}
+
static int sifive_l2_probe(struct device_d *dev)
{
struct resource *iores;
@@ -97,6 +114,8 @@ static int sifive_l2_probe(struct device_d *dev)
l2_base = IOMEM(iores->start);
+ sifive_l2_enable_ways();
+
dev->info = sifive_l2_config_read;
return 0;
--
2.29.2
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