With the different drivers now in place, we have everything to start a barebox image. Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx> --- Documentation/boards/riscv.rst | 37 + arch/riscv/Kconfig.socs | 18 + arch/riscv/boards/Makefile | 1 + arch/riscv/boards/beaglev/Makefile | 5 + arch/riscv/boards/beaglev/board.c | 30 + .../beaglev/defaultenv-beaglev/boot/buildroot | 13 + .../beaglev/defaultenv-beaglev/boot/fedora | 16 + .../defaultenv-beaglev/nv/boot.default | 1 + arch/riscv/boards/beaglev/lowlevel.c | 18 + arch/riscv/configs/starfive_defconfig | 131 +++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/jh7100-beaglev-starlight.dts | 54 ++ arch/riscv/dts/jh7100-beaglev-starlight.dtsi | 369 ++++++++ arch/riscv/dts/jh7100.dtsi | 798 ++++++++++++++++++ arch/riscv/include/asm/debug_ll.h | 3 + common/Kconfig | 5 + images/Makefile.riscv | 4 + 17 files changed, 1504 insertions(+) create mode 100644 arch/riscv/boards/beaglev/Makefile create mode 100644 arch/riscv/boards/beaglev/board.c create mode 100755 arch/riscv/boards/beaglev/defaultenv-beaglev/boot/buildroot create mode 100755 arch/riscv/boards/beaglev/defaultenv-beaglev/boot/fedora create mode 100644 arch/riscv/boards/beaglev/defaultenv-beaglev/nv/boot.default create mode 100644 arch/riscv/boards/beaglev/lowlevel.c create mode 100644 arch/riscv/configs/starfive_defconfig create mode 100644 arch/riscv/dts/jh7100-beaglev-starlight.dts create mode 100644 arch/riscv/dts/jh7100-beaglev-starlight.dtsi create mode 100644 arch/riscv/dts/jh7100.dtsi diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst index 53d13550f369..97f4d1deb7ba 100644 --- a/Documentation/boards/riscv.rst +++ b/Documentation/boards/riscv.rst @@ -60,6 +60,43 @@ into the config file. See https://barebox.org/jsbarebox/?graphic=1 for a live example. +BeagleV +------- + +barebox has second-stage support for the BeagleV Starlight:: + + make ARCH=riscv starfive_defconfig + make + +Thie resulting ``./images/barebox-beaglev-starlight.img`` can be used as payload +to opensbi:: + + git clone https://github.com/starfive-tech/opensbi + cd opensbi + export ARCH=riscv + export PLATFORM=starfive/vic7100 + export FW_PAYLOAD_PATH=$BAREBOX/build/images/barebox-beaglev-starlight.img + + make ARCH=riscv + ./fsz.sh ./build/platform/starfive/vic7100/firmware/fw_payload.bin fw_payload.bin.out + ls -l $OPENSBI/build/platform/starfive/vic7100/firmware/fw_payload.bin.out + +The resulting ``./platform/starfive/vic7100/firmware/fw_payload.bin.out`` can then +be flashed via Xmodem to the board:: + + picocom -b 115200 /dev/ttyUSB0 --send-cmd "sx -vv" --receive-cmd "rx -vv" + 0:update uboot + select the function: 0 + send file by xmodem + ^A^S./platform/starfive/vic7100/firmware/fw_payload.bin.out + +After reset, barebox should then boot to shell and attempt booting kernel ``Image`` +and device tree ``jh7100-starlight.dtb`` from the first root partition with the same +partition as rootfs. Note that while barebox does take over some initialization, +because of lack of Linux drivers, it doesn't yet do everything. If you experience +boot hangs, you may need to disable devices (or extend the starfive-pwrseq driver +to initialize it for you). + Erizo ----- diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index e5603b001c74..de74f216a215 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -50,6 +50,8 @@ endif config SOC_STARFIVE bool "StarFive SoCs" select ARCH_HAS_RESET_CONTROLLER + select RISCV_S_MODE + select HAS_ASM_DEBUG_LL help This enables support for SiFive SoC platform hardware. @@ -68,6 +70,22 @@ config SOC_STARFIVE_JH7100 with respect to DMA masters like GMAC and DW MMC controller. Select this if barebox needs to do DMA on this SoC. +config BOARD_BEAGLEV + bool "BeagleV" + depends on ARCH_RV64I + select SOC_STARFIVE_JH71XX + select USE_COMPRESSED_DTB + +config BOARD_BEAGLEV_BETA + bool "BeagleV Beta (with JH7100)" + depends on BOARD_BEAGLEV + select SOC_STARFIVE_JH7100 + help + Select this for hardware using the earlier JH7100 SoC. The JH7110 + used with later production runs is cache-coherent and thus can do + without the special DMA handling enabled by this option. It's safe + to enable this option for other SoCs. + endif comment "CPU features" diff --git a/arch/riscv/boards/Makefile b/arch/riscv/boards/Makefile index 99f22f32b470..cb28a25d8bc8 100644 --- a/arch/riscv/boards/Makefile +++ b/arch/riscv/boards/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo/ obj-$(CONFIG_BOARD_HIFIVE) += hifive/ +obj-$(CONFIG_BOARD_BEAGLEV) += beaglev/ diff --git a/arch/riscv/boards/beaglev/Makefile b/arch/riscv/boards/beaglev/Makefile new file mode 100644 index 000000000000..23efc273ee0a --- /dev/null +++ b/arch/riscv/boards/beaglev/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +pbl-y += lowlevel.o +obj-y += board.o +bbenv-y += defaultenv-beaglev diff --git a/arch/riscv/boards/beaglev/board.c b/arch/riscv/boards/beaglev/board.c new file mode 100644 index 000000000000..110754ea95fb --- /dev/null +++ b/arch/riscv/boards/beaglev/board.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + */ + +#include <common.h> +#include <driver.h> +#include <bbu.h> +#include <envfs.h> + +static int beaglev_probe(struct device_d *dev) +{ + barebox_set_hostname("beaglev-starlight"); + + defaultenv_append_directory(defaultenv_beaglev); + + return 0; +} + +static const struct of_device_id beaglev_of_match[] = { + { .compatible = "beagle,beaglev-starlight-jh7100" }, + { /* sentinel */ }, +}; + +static struct driver_d beaglev_board_driver = { + .name = "board-beaglev", + .probe = beaglev_probe, + .of_compatible = beaglev_of_match, +}; +device_platform_driver(beaglev_board_driver); diff --git a/arch/riscv/boards/beaglev/defaultenv-beaglev/boot/buildroot b/arch/riscv/boards/beaglev/defaultenv-beaglev/boot/buildroot new file mode 100755 index 000000000000..157223bbee45 --- /dev/null +++ b/arch/riscv/boards/beaglev/defaultenv-beaglev/boot/buildroot @@ -0,0 +1,13 @@ +#!/bin/sh + +BOOT=/mnt/mmc0.0/boot + +detect mmc0 + +global.linux.bootargs.base="rhgb stmmaceth=chain_mode:1" + +global.bootm.oftree=$BOOT/jh7100-starlight.dtb +global.bootm.image=$BOOT/Image +global linux.bootargs.root=rootwait +global linux.bootargs.earlycon=earlycon +global.bootm.appendroot=1 diff --git a/arch/riscv/boards/beaglev/defaultenv-beaglev/boot/fedora b/arch/riscv/boards/beaglev/defaultenv-beaglev/boot/fedora new file mode 100755 index 000000000000..4f9ab16f8233 --- /dev/null +++ b/arch/riscv/boards/beaglev/defaultenv-beaglev/boot/fedora @@ -0,0 +1,16 @@ +#!/bin/sh + +BOOT=/mnt/mmc0.0 +VERSION=5.10.6-210.0.riscv64.fc33.riscv64 + +detect mmc0 + +global.linux.bootargs.base="root=UUID=ae1e722a-d01b-4cdc-ab56-7b68abcdd0fe rhgb stmmaceth=chain_mode:1 selinux=0 LANG=en_US.UTF-8" + +global.bootm.oftree=${BOOT}/starfive_vic7100_beagle_v.dtb +global.bootm.initrd=${BOOT}/initramfs-${VERSION}.img +global.bootm.image=${BOOT}/vmlinuz-${VERSION} +global linux.bootargs.root=rootwait +global linux.bootargs.earlycon=earlycon +#global.bootm.root_dev=mmc0.1 +#global.bootm.appendroot=1 diff --git a/arch/riscv/boards/beaglev/defaultenv-beaglev/nv/boot.default b/arch/riscv/boards/beaglev/defaultenv-beaglev/nv/boot.default new file mode 100644 index 000000000000..880a6b1d8cf2 --- /dev/null +++ b/arch/riscv/boards/beaglev/defaultenv-beaglev/nv/boot.default @@ -0,0 +1 @@ +buildroot net diff --git a/arch/riscv/boards/beaglev/lowlevel.c b/arch/riscv/boards/beaglev/lowlevel.c new file mode 100644 index 000000000000..cccb928bc8e9 --- /dev/null +++ b/arch/riscv/boards/beaglev/lowlevel.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <debug_ll.h> +#include <asm/barebox-riscv.h> + +ENTRY_FUNCTION(start_beaglev_starlight, a0, a1, a2) +{ + extern char __dtb_z_jh7100_beaglev_starlight_start[]; + void *fdt; + + debug_ll_init(); + putc_ll('>'); + + fdt = __dtb_z_jh7100_beaglev_starlight_start + get_runtime_offset(); + + barebox_riscv_supervisor_entry(0x84000000, SZ_512M, a0, fdt); +} diff --git a/arch/riscv/configs/starfive_defconfig b/arch/riscv/configs/starfive_defconfig new file mode 100644 index 000000000000..c4df2256f589 --- /dev/null +++ b/arch/riscv/configs/starfive_defconfig @@ -0,0 +1,131 @@ +CONFIG_ARCH_RV64I=y +CONFIG_SOC_STARFIVE=y +CONFIG_BOARD_BEAGLEV=y +CONFIG_BOARD_BEAGLEV_BETA=y +CONFIG_BOARD_RISCV_GENERIC_DT=y +CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_STACK_SIZE=0x20000 +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_PANIC_HANG=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_BOOTM_INITRD=y +CONFIG_SYSTEM_PARTITIONS=y +CONFIG_IMD_TARGET=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_PBL_CONSOLE=y +CONFIG_PARTITION_DISK_EFI=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_BAREBOXENV_TARGET=y +CONFIG_BAREBOXCRC32_TARGET=y +CONFIG_STATE=y +CONFIG_STATE_CRYPTO=y +CONFIG_BOOTCHOOSER=y +CONFIG_RESET_SOURCE=y +CONFIG_MACHINE_ID=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_POLLER=y +CONFIG_CMD_SLICE=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_BOOTCHOOSER=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_CMP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_WD=y +CONFIG_CMD_2048=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_DIFF=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_DISPLAY_TIMINGS=y +CONFIG_CMD_OF_FIXUP_STATUS=y +CONFIG_CMD_OF_OVERLAY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_NET_DESIGNWARE=y +CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y +CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE=y +CONFIG_MICREL_PHY=y +CONFIG_SPI_MEM=y +CONFIG_DRIVER_SPI_GPIO=y +CONFIG_MCI=y +CONFIG_MCI_DW=y +CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 +CONFIG_SRAM=y +CONFIG_STARFIVE_PWRSEQ=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y +CONFIG_WATCHDOG=y +CONFIG_STARFIVE_WDT=y +CONFIG_HWRNG=y +CONFIG_HW_RANDOM_STARFIVE=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_STARFIVE=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_NVMEM=y +CONFIG_NVMEM_RMEM=y +CONFIG_STARFIVE_OTP=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_NVMEM_REBOOT_MODE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +# CONFIG_VIRTIO_MENU is not set +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UIMAGEFS=y +CONFIG_FS_PSTORE=y +CONFIG_FS_SQUASHFS=y +CONFIG_ZLIB=y +CONFIG_BZLIB=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DECOMPRESS=y +CONFIG_BASE64=y +CONFIG_DIGEST_CRC32_GENERIC=y diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 17fdc9445bd0..4a15423b7fc7 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -7,5 +7,6 @@ obj- += dummy.o pbl-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \ hifive-unleashed-a00.dtb.o +pbl-$(CONFIG_BOARD_BEAGLEV) += jh7100-beaglev-starlight.dtb.o clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts diff --git a/arch/riscv/dts/jh7100-beaglev-starlight.dts b/arch/riscv/dts/jh7100-beaglev-starlight.dts new file mode 100644 index 000000000000..8b4c1ac0eaa4 --- /dev/null +++ b/arch/riscv/dts/jh7100-beaglev-starlight.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "jh7100-beaglev-starlight.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "beagle,beaglev-starlight-jh7100", "starfive,jh7100"; + model = "BeagleV Starlight Beta"; + + aliases { + serial0 = &uart3; + serial1 = &uart0; + }; + + chosen { + environment { + compatible = "barebox,environment"; + device-path = &qpsi_env; + status = "disabled"; /* QSPI writes don't work yet */ + }; + }; +}; + +&nor_flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "secondboot"; + reg = <0x0 0x10000>; + }; + + partition@10000 { + label = "ddrinit"; + reg = <0x10000 0x10000>; + }; + + partition@20000 { + label = "sbi"; + reg = <0x20000 0x1e0000>; + }; + + qpsi_env: partition@200000 { + label = "environment"; + reg = <0x200000 0x1e00000>; + }; + }; +}; diff --git a/arch/riscv/dts/jh7100-beaglev-starlight.dtsi b/arch/riscv/dts/jh7100-beaglev-starlight.dtsi new file mode 100644 index 000000000000..13238f087f16 --- /dev/null +++ b/arch/riscv/dts/jh7100-beaglev-starlight.dtsi @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "jh7100.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "beagle,beaglev-starlight-jh7100", "starfive,jh7100"; + model = "BeagleV Starlight Beta"; + + aliases { + serial0 = &uart3; + serial1 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + cpus { + timebase-frequency = <6250000>; + }; + + gpiopof: gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "beaglev:green:ack"; + gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x0>; + }; + + memory@3000000000 { + device_type = "memory"; + reg = <0x30 0x0 0x0 0x0>; + }; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii>; + phy-mode = "rgmii-txid"; + nvmem-cell-names = "mac-address"; + nvmem-cells = <ðaddr>; +}; + +&gpio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; +}; + +&sdio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdio0>; + bus-width = <4>; + cap-sd-highspeed; + broken-cd; + no-sdio; + status = "okay"; +}; + +&sdio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdio1>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usb3 { + dr_mode = "host"; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + imx219@10 { + compatible = "imx219"; + reg = <0x10>; + reset-gpio = <&gpio 58 0>; + }; + + tps65086@5e { + compatible = "ti,tps65086"; + reg = <0x5e>; + gpio-controller; + #gpio-cells = <2>; + }; + + tda998x@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + seeed_plane_i2c@45 { + compatible = "seeed_panel"; + reg = <0x45>; + }; +}; + +&qspi { + nor_flash: nor-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <31250000>; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + status = "okay"; + + spi_dev0: spi@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <10000000>; + reg = <0>; + status = "okay"; + }; +}; + +&qspi { + status = "okay"; +}; + +&spi2 { + status = "okay"; +}; + +&otp { + power-gpios = <&gpio 56 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + + ethaddr: ethaddr@28 { + reg = <0x28 6>; + label = "mac-address"; + }; +}; + +&gpio { + pinctrl_uart0: uart0_pins { + pinctrl-single,pins = < + 0x358 0x2a /* GPIO40: uart0_pad_sin */ + 0x194 0x1 /* GPIO40: doen_HIGH */ + 0x198 0x7f /* GPIO41: dout_uart0_pad_sout */ + 0x19c 0x0 /* GPIO41: doen_LOW */ + 0x1a0 0x7e /* GPIO42: dout_uart0_pad_rtsn */ + 0x1a4 0x0 /* GPIO42: doen_LOW */ + 0x348 0x29 /* GPIO39: uart0_pad_ctsn */ + 0x18c 0x1 /* GPIO39: doen_HIGH */ + 0x16c 0x0 /* GPIO35: doen_LOW */ + 0x168 0x1 /* GPIO35: dout_HIGH */ + >; + }; + + pinctrl_i2c0: i2c0_pins { + pinctrl-single,pins = < + 0x240 0x0 /* GPIO62: dout_LOW */ + 0x238 0x0 /* GPIO61: dout_LOW */ + 0x244 0x80000008 /* GPIO62: doen_i2c0_pad_sck_oe + doen_reverse_(1) */ + 0x23c 0x80000009 /* GPIO61: doen_i2c0_pad_sda_oe + doen_reverse_(1) */ + 0x278 0x40 /* GPIO62: i2c0_pad_sck_in */ + 0x27c 0x3f /* GPIO61: i2c0_pad_sda_in */ + >; + }; + + pinctrl_i2c1: i2c1_pins { + pinctrl-single,pins = < + 0x1c8 0x0 /* GPIO47: dout_LOW */ + 0x1d0 0x0 /* GPIO48: dout_LOW */ + 0x1cc 0x8000000a /* GPIO47: doen_i2c1_pad_sck_oe + doen_reverse_(1) */ + 0x1d4 0x8000000b /* GPIO48: doen_i2c1_pad_sda_oe + doen_reverse_(1) */ + 0x280 0x31 /* GPIO47: i2c1_pad_sck_in */ + 0x284 0x32 /* GPIO48: i2c1_pad_sda_in */ + >; + }; + + pinctrl_i2c2: i2c2_pins { + pinctrl-single,pins = < + 0x230 0x0 /* GPIO60: dout_LOW */ + 0x228 0x0 /* GPIO59: dout_LOW */ + 0x234 0x8000000c /* GPIO60: doen_i2c2_pad_sck_oe + doen_reverse_(1) */ + 0x22c 0x8000000d /* GPIO59: doen_i2c2_pad_sda_oe + doen_reverse_(1) */ + 0x288 0x3e /* GPIO60: i2c2_pad_sck_in */ + 0x28c 0x3d /* GPIO59: i2c2_pad_sda_in */ + >; + }; + + pinctrl_spi2: spi2_pins { + pinctrl-single,pins = < + /* MISO */ + 0xa8 0x6f /* GPIO11: dout_spi2_pad_txd */ + 0xac 0x0 /* GPIO11: doen_LOW */ + /* MOSI */ + 0x320 0xe /* GPIO12: spi2_pad_rxd */ + 0xb4 0x1 /* GPIO12: doen_HIGH */ + /* SCLK */ + 0xe0 0x6c /* GPIO18: dout_spi2_pad_sck_out */ + 0xe4 0x0 /* GPIO18: doen_LOW */ + /* CS */ + 0xe8 0x6d /* GPIO19: dout_spi2_pad_ss_0_n */ + 0xec 0x0 /* GPIO19: doen_LOW */ + >; + + }; + + pinctrl_sdio0: sdio0_pins { + pinctrl-single,pins = < + 0x2b4 0x39 /* GPIO55: sdio0_pad_card_detect_n */ + 0x20c 0x1 /* GPIO55: doen_HIGH */ + 0x200 0x36 /* GPIO54: dout_sdio0_pad_cclk_out */ + 0x204 0x0 /* GPIO54: doen_LOW */ + 0x1fc 0x80000037 /* GPIO53: doen_sdio0_pad_ccmd_oe + doen_reverse_(1) */ + 0x1f8 0x38 /* GPIO53: dout_sdio0_pad_ccmd_out */ + 0x2bc 0x37 /* GPIO53: _sdio0_pad_ccmd_in */ + 0x1dc 0x80000039 /* GPIO49: doen_sdio0_pad_cdata_oe_bit0 + doen_reverse_(1) */ + 0x1d8 0x41 /* GPIO49: dout_sdio0_pad_cdata_out_bit0 */ + 0x2c0 0x33 /* GPIO49: sdio0_pad_cdata_in_bit0 */ + 0x1e4 0x8000003a /* GPIO50: doen_sdio0_pad_cdata_oe_bit1 + doen_reverse_(1) */ + 0x1e0 0x42 /* GPIO50: dout_sdio0_pad_cdata_out_bit1 */ + 0x2c4 0x34 /* GPIO50: sdio0_pad_cdata_in_bit1 */ + 0x1ec 0x8000003b /* GPIO51: doen_sdio0_pad_cdata_oe_bit2 + doen_reverse_(1) */ + 0x1e8 0x43 /* GPIO51: dout_sdio0_pad_cdata_out_bit2 */ + 0x2c8 0x35 /* GPIO51: sdio0_pad_cdata_in_bit2 */ + 0x1f4 0x8000003c /* GPIO52: doen_sdio0_pad_cdata_oe_bit3 + doen_reverse_(1) */ + 0x1f0 0x44 /* GPIO52: dout_sdio0_pad_cdata_out_bit3 */ + 0x2cc 0x36 /* GPIO52: sdio0_pad_cdata_in_bit3(52) */ + >; + }; + + pinctrl_sdio1: sdio1_pins { + pinctrl-single,pins = < + 0x158 0x4b /* GPIO33: dout_sdio1_pad_cclk_out */ + 0x15c 0x0 /* GPIO33: doen_LOW */ + 0x13c 0x8000004c /* GPIO29: doen_sdio1_pad_ccmd_oe + doen_reverse_(1) */ + 0x138 0x4d /* GPIO29: dout_sdio1_pad_ccmd_out */ + 0x2e8 0x1f /* GPIO29: sdio1_pad_ccmd_in */ + 0x174 0x8000004e /* GPIO36: doen_sdio1_pad_cdata_oe_bit0 + doen_reverse_(1) */ + 0x170 0x56 /* GPIO36: dout_sdio1_pad_cdata_out_bit0 */ + 0x2ec 0x26 /* GPIO36: sdio1_pad_cdata_in_bit0 */ + 0x144 0x8000004f /* GPIO30: doen_sdio1_pad_cdata_oe_bit1 + doen_reverse_(1) */ + 0x140 0x57 /* GPIO30: dout_sdio1_pad_cdata_out_bit1 */ + 0x2f0 0x20 /* GPIO30: sdio1_pad_cdata_in_bit1 */ + 0x164 0x80000050 /* GPIO34: doen_sdio1_pad_cdata_oe_bit2 + doen_reverse_(1) */ + 0x160 0x58 /* GPIO34: dout_sdio1_pad_cdata_out_bit2 */ + 0x2f4 0x24 /* GPIO34: sdio1_pad_cdata_in_bit2 */ + 0x14c 0x80000051 /* GPIO31: doen_sdio1_pad_cdata_oe_bit3 + doen_reverse_(1) */ + 0x148 0x59 /* GPIO31: dout_sdio1_pad_cdata_out_bit3 */ + 0x2f8 0x21 /* GPIO31: sdio1_pad_cdata_in_bit3 */ + >; + }; +}; + +&pinconf { + pinctrl_rgmii: rgmii_pins { + pinctrl-single,pins = < + 0x164 0xC30080 + 0x168 0x30080 + + 0x16c 0x30003 + 0x170 0x30003 + 0x174 0x30003 + 0x178 0x30003 + + 0x17c 0xC800003 + + 0x180 0x8000C0 + 0x184 0xC000C0 + 0x188 0xC000C0 + 0x18c 0xC000C0 + 0x190 0xC000C0 + 0x194 0xC000C0 + 0x198 0xC000C0 + >; + }; + + /* Force most pins to input. Taken from vendor's sys_funcshare_io_input_en */ + pinctrl_gpio: gpio_pins { + pinctrl-single,pins = < + 0x80 0xc000c0 /* gpio0 */ + 0x90 0xc000c0 /* gpio8-9 */ + 0x94 0xc000c0 /* gpio10-11 */ + 0x98 0xc000c0 /* gpio12 */ + 0xa0 0xc000c0 /* gpio16-17 */ + 0xa4 0xc000c0 /* gpio18-19 */ + 0xa8 0xc000c0 /* gpio20-21 */ + 0xac 0xc000c0 /* gpio22-23 */ + 0xb0 0xc000c0 /* gpio24-25 */ + 0xb4 0xc000c0 /* gpio26-27 */ + 0xb8 0xc000c0 /* gpio28-29 */ + 0xbc 0xc000c0 /* gpio30-31 */ + 0xc0 0xc000c0 /* gpio32-33 */ + 0xc4 0xc000c0 /* gpio34-35 */ + 0xcc 0xc000c0 /* gpio38-39 */ + 0xd0 0xc000c0 /* gpio40-41 */ + 0xd4 0xc000c0 /* gpio42-43 */ + 0xd8 0xc000c0 /* gpio44-45 */ + 0xdc 0xc000c0 /* gpio46-47 */ + 0xe0 0xc000c0 /* gpio48-49 */ + 0xe4 0xc000c0 /* gpio50-51 */ + 0xe8 0xc000c0 /* gpio52-53 */ + 0xec 0xc000c0 /* gpio54-55 */ + 0xf0 0xc000c0 /* gpio56-57 */ + 0xf4 0xc000c0 /* gpio58-59 */ + 0xf8 0xc000c0 /* gpio60-61 */ + 0xfc 0xc000c0 /* gpio62-63 */ + >; + }; +}; diff --git a/arch/riscv/dts/jh7100.dtsi b/arch/riscv/dts/jh7100.dtsi new file mode 100644 index 000000000000..e3990582af97 --- /dev/null +++ b/arch/riscv/dts/jh7100.dtsi @@ -0,0 +1,798 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/reset-controller/starfive-jh7100.h> +#include <dt-bindings/clock/starfive-jh7100.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "starfive,jh7100"; + + aliases { + spi0 = &qspi; + mmc0 = &sdio0; + mmc1 = &sdio1; + usb0 = &usb3; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "sifive,u74-mc", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0>; + riscv,isa = "rv64imafdc"; + starfive,itim = <&itim0>; + status = "okay"; + tlb-split; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <1>; + riscv,isa = "rv64imafdc"; + starfive,itim = <&itim1>; + status = "okay"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + osc_sys: clock-osc-sys { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc_sys"; + }; + + osc_aud: clock-osc-audio { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "osc_aud"; + }; + + i2c0clk: i2c0clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <49500000>; + clock-output-names = "i2c0clk"; + }; + + i2c2clk: i2c2clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <49500000>; + clock-output-names = "i2c2clk"; + }; + + axiclk: axiclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <500000000>; + clock-output-names = "axiclk"; + }; + + ahb0clk: ahb0clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <250000000>; + }; + + apb1clk: apb1clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; + + apb2clk: apb2clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; + + jpuclk: jpuclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <333333333>; + }; + + vpuclk: vpuclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <400000000>; + }; + + qspi_clk: qspi-clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uartclk: uartclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + hs_uartclk: hs_uartclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <74250000>; + }; + + spiclk: spiclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + pwmclk: pwmclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x28000000>; + alignment = <0x0 0x1000>; + alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>; + linux,cma-default; + }; + + jpu_reserved: framebuffer@c9000000 { + reg = <0x0 0xc9000000 0x0 0x4000000>; + }; + + nvdla_reserved:framebuffer@d0000000 { + reg = <0x0 0xd0000000 0x0 0x28000000>; + }; + + vin_reserved: framebuffer@f9000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0xf9000000 0x0 0x1000000>; + }; + + sffb_reserved: framebuffer@fb000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0xfb000000 0x0 0x2000000>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + #clock-cells = <1>; + compatible = "simple-bus"; + ranges; + + intram0: sram@18000000 { + compatible = "mmio-sram"; + reg = <0x0 0x18000000 0x0 0x20000>; + }; + + intram1: sram@18080000 { + compatible = "mmio-sram"; + reg = <0x0 0x18080000 0x0 0x8000>; + }; + + ccache: cache-controller@2010000 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache"; + interrupt-parent = <&plic>; + interrupts = <128 131 129 130>; + /*next-level-cache = <&L40 &L36>;*/ + reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "sideband"; + }; + + dtim: dtim@1000000 { + compatible = "starfive,dtim0"; + reg = <0x0 0x1000000 0x0 0x2000>; + reg-names = "mem"; + }; + + itim0: itim@1808000 { + compatible = "starfive,itim0"; + reg = <0x0 0x1808000 0x0 0x8000>; + reg-names = "mem"; + }; + + itim1: itim@1820000 { + compatible = "starfive,itim0"; + reg = <0x0 0x1820000 0x0 0x8000>; + reg-names = "mem"; + }; + + clint: clint@2000000 { + #interrupt-cells = <1>; + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + }; + + plic: plic@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 &cpu1_intc 11 &cpu1_intc 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <127>; + }; + + sysmain: syscon@11850000 { + compatible = "syscon"; + reg = <0x0 0x11850000 0x0 0x4000>; + }; + + pinconf: pinctrl@11858000 { + compatible = "pinctrl-single"; + reg = <0x0 0x11858000 0x0 0x4000>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + uart0: hs_serial@11870000 { + compatible = "snps,dw-apb-uart"; + interrupt-parent = <&plic>; + interrupts = <92>; + reg = <0x0 0x11870000 0x0 0x10000>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&hs_uartclk>, <&apb1clk>; + clock-names = "baudclk", "apb_pclk"; + current-clock = <74250000>; + current-speed = <115200>; + status = "disabled"; + }; + + uart1: hs_serial@11880000 { + compatible = "snps,dw-apb-uart"; + interrupt-parent = <&plic>; + interrupts = <93>; + reg = <0x0 0x11880000 0x0 0x10000>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&hs_uartclk>, <&apb1clk>; + clock-names = "baudclk", "apb_pclk"; + current-clock = <74250000>; + current-speed = <115200>; + status = "disabled"; + }; + + uart2: serial@12430000 { + compatible = "snps,dw-apb-uart"; + interrupt-parent = <&plic>; + interrupts = <72>; + reg = <0x0 0x12430000 0x0 0x10000>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&uartclk>, <&apb2clk>; + clock-names = "baudclk", "apb_pclk"; + current-clock = <100000000>; + current-speed = <115200>; + status = "disabled"; + }; + + uart3: serial@12440000 { + compatible = "snps,dw-apb-uart", "starfive,uart0"; + interrupt-parent = <&plic>; + interrupts = <73>; + reg = <0x0 0x12440000 0x0 0x10000>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&uartclk>, <&apb2clk>; + clock-names = "baudclk", "apb_pclk"; + current-clock = <100000000>; + current-speed = <115200>; + status = "disabled"; + }; + + nne50: nne@10800000 { + compatible = "starfive,nne50"; + reg = <0x0 0x10800000 0x0 0x10000>; + resets = <&rstgen RSTN_DLA_AXI>, + <&rstgen RSTN_DLANOC_AXI>, + <&rstgen RSTN_DLA_APB>, + <&rstgen RSTN_NNENOC_AXI>, + <&rstgen RSTN_DLASLV_AXI>; + + assigned-clocks = <&clkgen CLK_NNE_BUS>; + assigned-clocks-parents = <&clkgen CLK_CPU_AXI>; + status = "okay"; + }; + + dma2p: sgdma2p@100b0000 { + compatible = "starfive,axi-dma", "snps,axi-dma-1.01a"; + reg = <0x0 0x100b0000 0x0 0x10000>; + clocks = <&axiclk>, <&ahb0clk>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&rstgen RSTN_DMA2PNOC_AXI>, <&rstgen RSTN_SGDMA2P_AXI>, <&rstgen RSTN_SGDMA2P_AHB>; + reset-names = "noc", "axi", "ahb"; + interrupt-parent = <&plic>; + interrupts = <2>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <128>; + status = "okay"; + }; + + dma1p: sgdma1p@10500000 { + compatible = "starfive,axi-dma", "snps,axi-dma-1.01a"; + reg = <0x0 0x10500000 0x0 0x10000>; + clocks = <&axiclk>, <&ahb0clk>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&rstgen RSTN_SGDMA1P_AXI>; + interrupt-parent = <&plic>; + interrupts = <1>; + dma-channels = <16>; + snps,dma-masters = <1>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>; + snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + snps,axi-max-burst-len = <64>; + status = "okay"; + }; + + usb3: usb@104c0000 { + compatible = "cdns,usb3"; + reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers + <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers + <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers + reg-names = "otg", "xhci", "dev"; + interrupt-parent = <&plic>; + interrupts = <43>, <44>, <52>; + interrupt-names = "otg", + "host", + "peripheral"; + phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy"; + maximum-speed = "super-speed"; + status = "disabled"; + }; + + gpio: gpio@11910000 { + compatible = "starfive,gpio0"; + interrupt-parent = <&plic>; + interrupts = <32>; + resets = <&rstgen RSTN_GPIO_APB>; + clocks = <&clkgen CLK_GPIO_APB>; + reg = <0x0 0x11910000 0x0 0x10000>; + reg-names = "control"; + interrupt-controller; + #gpio-cells = <2>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + i2c0: i2c@118b0000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x118b0000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <96>; + clocks = <&i2c0clk>; + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <500>; + i2c-scl-falling-time-ns = <500>; + scl-gpio = <&gpio 62 0>; + sda-gpio = <&gpio 61 0>; + status = "disabled"; + }; + + i2c1: i2c@118c0000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x118c0000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <97>; + clocks = <&i2c0clk>; + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <100>; + i2c-scl-falling-time-ns = <100>; + scl-gpio = <&gpio 47 0>; + sda-gpio = <&gpio 48 0>; + status = "disabled"; + }; + + i2c2: i2c@12450000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x12450000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <74>; + clocks = <&i2c2clk>; + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <500>; + i2c-scl-falling-time-ns = <500>; + scl-gpio = <&gpio 60 0>; + sda-gpio = <&gpio 59 0>; + status = "disabled"; + }; + + trng: trng@118d0000 { + compatible = "starfive,vic-rng"; + reg = <0x0 0x118d0000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <98>; + clocks = <&clkgen CLK_TRNG_APB>; + resets = <&rstgen RSTN_TRNG_APB>; + }; + + crypto: crypto@100d0000 { + compatible = "starfive,vic-sec"; + reg = <0x0 0x100d0000 0x0 0x20000>, + <0x0 0x11800234 0x0 0xc>; + reg-names = "secmem", "secclk"; + resets = <&rstgen RSTN_SEC_AHB>, <&rstgen RSTN_AES>, + <&rstgen RSTN_PKA>, <&rstgen RSTN_SHA>; + interrupt-parent = <&plic>; + interrupts = <31>; + clocks = <&osc_sys>; + }; + + /* gmac device configuration */ + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <256 128 64 32 0 0 0>; + }; + + gmac: gmac@10020000 { + compatible = "starfive,stmmac"; + reg = <0x0 0x10020000 0x0 0x10000>; + interrupt-parent = <&plic>; + interrupts = <6 7>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&rstgen RSTN_GMAC_AHB>; + reset-names = "stmmaceth"; + clocks = <&clkgen CLK_GMAC_AHB>, <&clkgen CLK_GMAC_PTP_REF>, + <&clkgen CLK_GMAC_GTX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + max-frame-size = <9000>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <32768>; + tx-fifo-depth = <16384>; + snps,fixed-burst = <1>; + snps,no-pbl-x8 = <1>; + /*snps,force_sf_dma_mode;*/ + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + starfive,sysmain = <&sysmain>; + }; + + nbdla: nvdla@11940000 { + compatible = "nvidia,nvdla_os_initial"; + interrupt-parent = <&plic>; + resets = <&rstgen RSTN_DLA_AXI>, + <&rstgen RSTN_DLANOC_AXI>, + <&rstgen RSTN_DLA_APB>, + <&rstgen RSTN_NNENOC_AXI>, + <&rstgen RSTN_DLASLV_AXI>; + interrupts = <22>; + memory-region = <&nvdla_reserved>; + reg = <0x0 0x11940000 0x0 0x40000>; + status = "okay"; + }; + + jpu: coadj12@11900000 { + compatible = "cm,codaj12-jpu-1"; + reg = <0x0 0x11900000 0x0 0x300>; + memory-region = <&jpu_reserved>; + interrupt-parent = <&plic>; + interrupts = <24>; + clocks = <&jpuclk>; + clock-names = "jpege"; + reg-names = "control"; + resets = <&rstgen RSTN_JPEG_AXI>, <&rstgen RSTN_JPEG_CCLK>, + <&rstgen RSTN_JPEG_APB>; + status = "okay"; + }; + + clkgen: clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x0 0x11800000 0x0 0x10000>; + clocks = <&osc_sys>, <&osc_aud>; + clock-names = "osc_sys", "osc_aud"; + #clock-cells = <1>; + }; + + vpu_dec: vpu_dec@118f0000 { + compatible = "cm,cm511-vpu"; + reg = <0 0x118f0000 0 0x10000>; + //memory-region = <&vpu_reserved>; + interrupt-parent = <&plic>; + interrupts = <23>; + clocks = <&vpuclk>; + clock-names = "vcodec"; + resets = <&rstgen RSTN_VDEC_AXI>, <&rstgen RSTN_VDECBRG_MAIN>, + <&rstgen RSTN_VDEC_BCLK>, <&rstgen RSTN_VDEC_CCLK>, + <&rstgen RSTN_VDEC_APB>; + status = "okay"; + }; + + vpu_enc: vpu_enc@118e0000 { + compatible = "cm,cm521-vpu"; + reg = <0x0 0x118e0000 0x0 0x4000>; + interrupt-parent = <&plic>; + interrupts = <26>; + clocks = <&vpuclk>; + clock-names = "vcodec"; + resets = <&rstgen RSTN_VENC_AXI>, <&rstgen RSTN_VENCBRG_MAIN>, + <&rstgen RSTN_VENC_BCLK>, <&rstgen RSTN_VENC_CCLK>, + <&rstgen RSTN_VENC_APB>; + reg-names = "control"; + }; + + wdt: watchdogm@12480000 { + compatible = "starfive,wdt"; + reg = <0x0 0x12480000 0x0 0x10000>; + clocks = <&clkgen CLK_WDTIMER_APB>,<&clkgen CLK_WDT_CORE>; + clock-names = "bus", "core"; + resets = <&rstgen RSTN_WDTIMER_APB>, <&rstgen RSTN_WDT>; + reset-names = "bus", "core"; + }; + + ptc: pwm@12490000 { + compatible = "starfive,pwm0"; + reg = <0x0 0x12490000 0x0 0x10000>; + reg-names = "control"; + sifive,approx-period = <100000000>; + clocks = <&pwmclk>; + #pwm-cells = <3>; + sifive,npwm = <8>; + + }; + + rstgen: reset-controller@11840000 { + compatible = "starfive,jh7100-rstgen"; + reg = <0x0 0x11840000 0x0 0x10000>; + #reset-cells = <1>; + }; + + spi2ahb { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "starfive,spi2ahb"; + resets = <&rstgen RSTN_SPI2AHB_AHB>, <&rstgen RSTN_SPI2AHB_CORE>; + + qspi: spi@11860000 { + compatible = "cadence,qspi", "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000>; + interrupts = <3>; + interrupt-parent = <&plic>; + clocks = <&qspi_clk>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + status = "disabled"; + spi-max-frequency = <250000000>; + }; + + spi2: spi@12410000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <70>; + reg = <0x0 0x12410000 0x0 0x10000>; + clocks = <&spiclk>; + status = "disabled"; + /* + num-cs = <1>; + cs-gpios = <&gpio 0 0>; + */ + }; + }; + + xrp@f0000000 { + compatible = "cdns,xrp"; + reg = <0x0 0xf0000000 0x0 0x01ffffff + 0x10 0x72000000 0x0 0x00001000 + 0x10 0x72001000 0x0 0x00fff000 + 0x0 0x124b0000 0x0 0x00010000>; + clocks = <&osc_sys>; + interrupt-parent = <&plic>; + firmware-name = "vp6_elf"; + resets = <&rstgen RSTN_VP6INTC_APB>; + dsp-irq = <19 20>; + dsp-irq-src = <0x20 0x21>; + intc-irq-mode = <1>; + intc-irq = <0 1>; + interrupts = <27 28>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x0 0x40000000 0x01000000 + 0xb0000000 0x10 0x70000000 0x3000000>; + dsp@0 { + }; + }; + + sdio0: sdio0@10000000 { + compatible = "starfive,jh7100-dw-mshc", "snps,dw-mshc"; + reg = <0x0 0x10000000 0x0 0x10000>; + interrupts = <4>; + interrupt-parent = <&plic>; + clocks = <&clkgen CLK_SDIO0_AHB>, <&clkgen CLK_SDIO0_CCLKINT>; + clock-names = "biu", "ciu"; + resets = <&rstgen RSTN_SDIO0_AHB>; + reset-names = "reset"; + clock-frequency = <100000000>; + max-frequency = <10000000>; + fifo-depth = <32>; + card-detect-delay = <300>; + fifo-watermark-aligned; + data-addr = <0>; + post-power-on-delay-ms = <200>; + status = "disabled"; + }; + + sdio1: sdio1@10010000 { + compatible = "starfive,jh7100-dw-mshc", "snps,dw-mshc"; + reg = <0x0 0x10010000 0x0 0x10000>; + interrupts = <5>; + interrupt-parent = <&plic>; + clocks = <&clkgen CLK_SDIO1_AHB>, <&clkgen CLK_SDIO1_CCLKINT>; + clock-names = "biu", "ciu"; + resets = <&rstgen RSTN_SDIO1_AHB>; + reset-names = "reset"; + clock-frequency = <100000000>; + max-frequency = <10000000>; + fifo-depth = <32>; + card-detect-delay = <300>; + fifo-watermark-aligned; + data-addr = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + cap-mmc-hw-reset; + enable-sdio-wakeup; + keep-power-in-suspend; + cap-mmc-highspeed; + post-power-on-delay-ms = <200>; + status = "disabled"; + }; + + sfivefb: sfivefb@12000000 { + compatible = "starfive,vpp-lcdc"; + interrupt-parent = <&plic>; + interrupts = <101>, <103>; + interrupt-names = "lcdc_irq", "vpp1_irq"; + reg = <0x0 0x12000000 0x0 0x10000>, + <0x0 0x12100000 0x0 0x10000>, + <0x0 0x12040000 0x0 0x10000>, + <0x0 0x12080000 0x0 0x10000>, + <0x0 0x120c0000 0x0 0x10000>, + <0x0 0x12240000 0x0 0x10000>, + <0x0 0x12250000 0x0 0x10000>, + <0x0 0x12260000 0x0 0x10000>; + reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys"; + memory-region = <&sffb_reserved>; + clocks = <&uartclk>, <&apb2clk>; + clock-names = "baudclk", "apb_pclk"; + status = "okay"; + ddr-format = <4>;/* LCDC win_format WIN_FMT_RGB565 */ + }; + + vin_sysctl: vin_sysctl@19800000 { + compatible = "starfive,stf-vin"; + reg = <0x0 0x19800000 0x0 0x10000>, + <0x0 0x19810000 0x0 0x10000>, + <0x0 0x19820000 0x0 0x10000>, + <0x0 0x19830000 0x0 0x10000>, + <0x0 0x19840000 0x0 0x10000>, + <0x0 0x19870000 0x0 0x30000>, + <0x0 0x198a0000 0x0 0x30000>, + <0x0 0x11800000 0x0 0x10000>, + <0x0 0x11840000 0x0 0x10000>, + <0x0 0x11858000 0x0 0x10000>; + reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", + "isp0", "isp1", "tclk", "trst", "iopad"; + interrupt-parent = <&plic>; + interrupts = <119 109>; + memory-region = <&vin_reserved>; + /*defaule config for imx219 vin&isp*/ + format = <3>; /* SRC_CSI2RX_VIN_ISP */ + frame-width = <800>; + frame-height =<480>; + isp0_enable; + csi-lane = <2>; + csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>; + csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>; + csi-clane-swap = /bits/ 8 <0>; + csi-clane-pn-swap = /bits/ 8 <0>; + csi-mipiID = <0>; + csi-width = <1920>; + csi-height = <1080>; + csi-dt = <0x2b>; + }; + + sfc_tmp: tmpsensor@124a0000 { + compatible = "sfc,tempsensor"; + reg = <0x0 0x124a0000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <122>; + resets = <&rstgen RSTN_TEMP_APB>, <&rstgen RSTN_TEMP_SENSE>; + status = "okay"; + }; + + otp: otp@11810000 { + compatible = "starfive,fu740-otp"; + reg = <0x0 0x11810000 0x0 0x10000>; + fuse-count = <0x200>; + resets = <&rstgen RSTN_OTP_APB>; + clocks = <&clkgen CLK_OTP_APB>; + }; + }; +}; diff --git a/arch/riscv/include/asm/debug_ll.h b/arch/riscv/include/asm/debug_ll.h index 13609d25c559..b4caa0597a2d 100644 --- a/arch/riscv/include/asm/debug_ll.h +++ b/arch/riscv/include/asm/debug_ll.h @@ -17,6 +17,9 @@ #if defined CONFIG_DEBUG_ERIZO #define DEBUG_LL_UART_ADDR 0x90000000 #define DEBUG_LL_UART_CLK (24000000 / 16) +#elif defined CONFIG_DEBUG_STARFIVE +#define DEBUG_LL_UART_ADDR 0x12440000 +#define DEBUG_LL_UART_CLK (100000000 / 16) #endif #define DEBUG_LL_UART_SHIFT 2 diff --git a/common/Kconfig b/common/Kconfig index 98be9b58abce..d4e518bf8ade 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1378,6 +1378,11 @@ config DEBUG_ERIZO depends on SOC_ERIZO select DEBUG_LL_NS16550 +config DEBUG_STARFIVE + bool "Starfive ns16550 serial0 port" + depends on SOC_STARFIVE + select DEBUG_LL_NS16550 + config DEBUG_SIFIVE bool "SiFive serial0 port" depends on SOC_SIFIVE diff --git a/images/Makefile.riscv b/images/Makefile.riscv index c44c683431f7..4410765cf664 100644 --- a/images/Makefile.riscv +++ b/images/Makefile.riscv @@ -15,3 +15,7 @@ pblb-$(CONFIG_BOARD_HIFIVE) += start_hifive_unmatched start_hifive_unleashed FILE_barebox-hifive-unmatched.img = start_hifive_unmatched.pblb FILE_barebox-hifive-unleashed.img = start_hifive_unleashed.pblb image-$(CONFIG_BOARD_HIFIVE) += barebox-hifive-unmatched.img barebox-hifive-unleashed.img + +pblb-$(CONFIG_BOARD_BEAGLEV) += start_beaglev_starlight +FILE_barebox-beaglev-starlight.img = start_beaglev_starlight.pblb +image-$(CONFIG_BOARD_BEAGLEV) += barebox-beaglev-starlight.img -- 2.29.2 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
