I observed errors on the ZynqMP during reading the EXT_CSD registers using CMD8. The Zynq UltraScale+ Device TRM UG1085 (v2.2) p. 777 states that the driver shall wait 2 ms after sending CMD6 for setting a EXT_CSD register. The JEDEC Standard No. 84-A43 p. 35 does not specify the delay but states that CMD6 expects an R1b response and that the host has to wait until the busy signal is de-asserted. This is signaled via the SDHCI_INT_XFER_COMPLETE interrupt. Wait for the XFER_COMPLETE interrupt after sending a command that expects an R1b response. Signed-off-by: Michael Tretter <m.tretter@xxxxxxxxxxxxxx> --- drivers/mci/arasan-sdhci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mci/arasan-sdhci.c b/drivers/mci/arasan-sdhci.c index 732f838d8395..d45f9184cd1d 100644 --- a/drivers/mci/arasan-sdhci.c +++ b/drivers/mci/arasan-sdhci.c @@ -193,6 +193,8 @@ static int arasan_sdhci_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, mask = SDHCI_INT_CMD_COMPLETE; if (data && data->flags == MMC_DATA_READ) mask |= SDHCI_INT_DATA_AVAIL; + if (cmd->resp_type & MMC_RSP_BUSY) + mask |= SDHCI_INT_XFER_COMPLETE; sdhci_set_cmd_xfer_mode(&host->sdhci, cmd, data, false, &command, &xfer); -- 2.29.2 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
