Re: [PATCH v2 10/11] mips: Implement setjmp/longjmp/initjmp

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Hi, Sascha and Ahmad,

On Mon, Mar 01, 2021 at 12:01:05PM +0100, Ahmad Fatoum wrote:
> From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> 
> The header has been taken from glibc, the implementation itself is based
> on the newlib implementation.
> 
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
> ---
>  arch/mips/Kconfig              |  1 +
>  arch/mips/include/asm/setjmp.h | 32 ++++++++++++++++++++++
>  arch/mips/lib/Makefile         |  1 +
>  arch/mips/lib/setjmp.S         | 50 ++++++++++++++++++++++++++++++++++
>  4 files changed, 84 insertions(+)
>  create mode 100644 arch/mips/include/asm/setjmp.h
>  create mode 100644 arch/mips/lib/setjmp.S
> 
> ...
>
> diff --git a/arch/mips/lib/setjmp.S b/arch/mips/lib/setjmp.S
> new file mode 100644
> index 000000000000..b09a7c55293c
> --- /dev/null
> +++ b/arch/mips/lib/setjmp.S
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#include <asm/regdef.h>
> +#include <asm/asm.h>
> +#include <linux/linkage.h>
> +
> +/* int setjmp (jmp_buf);  */
> +LEAF(setjmp)
> +	sw	ra, (0 * 4)(a0)
> +	sw	sp, (1 * 4)(a0)
> +	sw	s0, (2 * 4)(a0)
> +	sw	s1, (3 * 4)(a0)
> +	sw	s2, (4 * 4)(a0)
> +	sw	s3, (5 * 4)(a0)
> +	sw	s4, (6 * 4)(a0)
> +	sw	s5, (7 * 4)(a0)
> +	sw	s6, (8 * 4)(a0)
> +	sw	s7, (9 * 4)(a0)
> +	sw	fp, (10 * 4)(a0)
> +	move	v0, zero
> +	j	ra
> +END(setjmp)
> +
> +/* volatile void longjmp (jmp_buf, int);  */
> +LEAF(longjmp)
> +	lw	ra, (0 * 4)(a0)
> +	lw	sp, (1 * 4)(a0)
> +	lw	s0, (2 * 4)(a0)
> +	lw	s1, (3 * 4)(a0)
> +	lw	s2, (4 * 4)(a0)
> +	lw	s3, (5 * 4)(a0)
> +	lw	s4, (6 * 4)(a0)
> +	lw	s5, (7 * 4)(a0)
> +	lw	s6, (8 * 4)(a0)
> +	lw	s7, (9 * 4)(a0)
> +	lw	fp, (10 * 4)(a0)
> +	bne	a1, zero, 1f
> +	li	a1, 1
> +1:
> +	move	v0, a1
> +	j	ra
> +END(longjmp)
> +
> +/* int initjmp(jmp_buf jmp, void __noreturn (*func)(void), void *stack_top); */
> +LEAF(initjmp)
> +	sw	a1, (0 * 4)(a0)
> +	sw	a2, (1 * 4)(a0)
> +	move	v0, zero
> +	j	ra
> +END(initjmp)

I would suggest using `REG_S/REG_L r, (n * SZREG)(a0)` here for the sake of 
MIPS64 targets. See arch/mips/include/asm/asm.h:272.

Regards,
Peter

> -- 
> 2.29.2
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@xxxxxxxxxxxxxxxxxxx
> http://lists.infradead.org/mailman/listinfo/barebox

_______________________________________________
barebox mailing list
barebox@xxxxxxxxxxxxxxxxxxx
http://lists.infradead.org/mailman/listinfo/barebox



[Index of Archives]     [Linux Embedded]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]     [XFree86]

  Powered by Linux