I fixed the problem by adding another chunk for the LDB node,
this will be a temporary solution for now:
&ldb {
assigned-clocks = <&clks IMX6QDL_CLK_PLL5_VIDEO>;
assigned-clock-parents = <0>;
assigned-clock-rates = <716800000>;
status = "okay";
...
Thanks All!
>Пятница, 13 ноября 2020, 14:01 +03:00 от Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>:
>Hello,
>On 11/13/20 9:51 AM, Alexander Shiyan wrote:
>> Hello All.
>> I am having problems updating the barebox from version 2019.02 to version 2020.10.
>> The barebox i.MX6 CLK driver now uses several patches compared to the previous
>> version to fix the err009219 bug, and the display no more works as before.
>> I use a board based on i.MX6Q revision 1.2. With the old bootloader, the LVDS channel
>> is initialized and I can display the splash screen in the barebox. After loading the kernel,
>> everything works too.
>> I added source selection for LVDS channels and the kernel works with these additions.
>> &clks {
>> assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
>> <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
>> assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
>> <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
>> };
>>
>> The splash screen in new version is not displayed in the barebox.
>> So, the question, what I do incorrect and how to fix this?
>> Old clk_dump:
>> pll5_video (rate 716800008, enabled)
>> pll5_post_div (rate 179200002, enabled)
>> pll5_video_div (rate 44800001, enabled)
>> ldb_di0_sel (rate 44800001, enabled)
>> ldb_di0_div_3_5 (rate 12800000, enabled)
>> ldb_di0_podf (rate 6400000, enabled)
>> ipu1_di0_sel (rate 6400000, enabled)
>> ipu1_di0 (rate 6400000, enabled)
>> 2400000.ipu@2400000.of_di0_pixel (rate 6400000, enabled)
>44800001 / 6400000 = 7.00000015625
>
>> ldb_di0 (rate 6400000, enabled)
>> New:
>> pll5_video (rate 716800008, enable_count: 1, unknown)
>> pll5_post_div (rate 358400004, enable_count: 1, always enabled)
>> pll5_video_div (rate 179200002, enable_count: 1, always enabled)
>> ldb_di0_sel (rate 179200002, enable_count: 1, always enabled)
>> ldb_di0_div_3_5 (rate 51200000, enable_count: 1, always enabled)
>> ldb_di0_podf (rate 25600000, enable_count: 1, always enabled)
>> ipu1_di0_sel (rate 25600000, enable_count: 1, always enabled)
>> ipu1_di0 (rate 25600000, enable_count: 1, enabled)
>> 2400000.ipu@2400000.of_di0_pixel (rate 6400000, enable_count: 1, always enabled)
>
>179200002 / 6400000 = 28.0000003125
>
>
>Shouldn't both be a clean 7.0? Is it normal that your PLL5 couldn't be configured
>exactly to 716800000?
>
>Does Linux /sys/kernel/debug/clk/clk_summary have the same frequencies?
>
>For comparison, I've a 33MHz display with the assigned-clock/assigned-clock-parents
>snippet in the barebox device tree, but not in the kernel's and it works for me:
>
>pll5_video (rate 924000000, enable_count: 1, unknown)
> pll5_post_div (rate 462000000, enable_count: 1, always enabled)
> pll5_video_div (rate 231000000, enable_count: 1, always enabled)
> ldb_di0_sel (rate 231000000, enable_count: 1, always enabled)
> ldb_di0_div_3_5 (rate 66000000, enable_count: 1, always enabled)
> ldb_di0_podf (rate 33000000, enable_count: 2, always enabled)
> ipu1_di0_sel (rate 33000000, enable_count: 1, always enabled)
> ipu1_di0 (rate 33000000, enable_count: 1, enabled)
> 2400000.ipu@2400000.of_di0_pixel (rate 16500000, enable_count: 1, always enabled)
> ipu2_di1_sel (rate 33000000, enable_count: 1, always enabled)
> ipu2_di1 (rate 33000000, enable_count: 1, enabled)
> 2800000.ipu@2800000.of_di1_pixel (rate 33000000, enable_count: 1, always enabled)
> ldb_di0 (rate 33000000, enable_count: 0, enabled)
> ldb_di1_sel (rate 231000000, enable_count: 0, always enabled)
> ldb_di1_div_3_5 (rate 66000000, enable_count: 0, always enabled)
> ldb_di1_podf (rate 33000000, enable_count: 0, always enabled)
> ldb_di1 (rate 33000000, enable_count: 0, enabled)
>
>
>> ldb_di0 (rate 25600000, enable_count: 0, enabled)
>>
>> Can anyone help me to resolve this?
---
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