On Tue, Nov 10, 2020 at 08:48:11AM +0100, Sascha Hauer wrote:
> On Tue, Nov 10, 2020 at 07:33:53AM +0100, Rouven Czerwinski wrote:
> > On Mon, 2020-11-09 at 14:52 +0100, Lucas Stach wrote:
> > > Am Montag, den 09.11.2020, 14:44 +0100 schrieb Rouven Czerwinski:
> > > > Annotate the different read and write functions with
> > > > zero_page_{access/faulting}. This allows the cfi_flash driver to be used
> > > > on the QEMU virt machine with an enabled MMU.
> > >
> > > I don't like this zero-page access allow in a driver at all. If you
> > > have some free address space somewhere, you could also solve this issue
> > > by remapping the IO resource to somewhere else in the address space,
> > > deviating from the 1:1 mapping. The Tegra PCIe host driver does this,
> > > if you need some inspiration.
> >
> > I totally agree, remapping the IO region sounds like a much better
> > choice.
>
> But where should it be mapped to? Just 4k upwards and hope that the area
> just above the cfi flash isn't occupied by something else?
Ok, here's the plan:
In a board specific initcall map the memory to wherever it's convenient,
modify the address of the CFI flash in the device node and add a big
comment that there's nothing to see here.
Sascha
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