This is a simple driver for the ADC. It's designed to get single
readings. Possible uses would be temperature sensing a thermistor,
measuring a power rail, or a detecting multi-level board ID pin
strapping.
It's not designed to co-exist with a touch screen controller driver,
which uses the same hardware on the AM335x, as there is no barebox
touchscreen driver.
The device tree binding is compatible with the Linux IIO driver.
This is from the Linux driver:
The ADC clock is expected to run at target of 3MHz, and expected to
capture 12-bit data at a rate of 200 KSPS. The TSC_ADC_SS
controller design assumes the OCP clock is at least 6x faster than
the ADC clock.
The OCP clock is 100 MHz, from CORE_CLKOUTM4/2. The AM335x Reference
Manual §12.2.2 gives a max ADC clock of 24 MHz. There's nothing about
the factor of 6x OCP to ADC, a 3 MHz ADC target, nor 200 kSPS. In
§12.3.7 a limit of at least 15 ADC clock cycles per sample is given.
The AM335x Datasheet §5.10 provides more parameters for the ADC: An ADC
clock max of 3 MHz, a nominal conversion time of 13 cycles, min and max
acquisition time of 2 to 257 cycles, and a max sample rate (@ 3 MHz) of
200 kSPS.
A 3 MHz ADC clock at 15 cycles per sample provides for a 200 kSPS
sampling rate. The minimum open, sampling, and conversion times are 0,
1, and 13 clocks, respectively. This would seem to indicate the
sampling at 14 cyles per sample is possible. Perhaps the "Sample Delay"
in the reference manual is called "Acquisition Time" in the datasheet,
and the reference manual minimum of 1 cycle is incorrect and the minimum
is actually 2 cycles. Which would then produce a minimum of 15 cycles
per sample.
This driver assumes the external references will be used (as does the
Linux IIO driver). This would have been good to put into the device
tree bindings, but the Linux driver's bindings did not do that.
The Barebox driver will convert the ADC reading to mV, and assumes the
external refs are GND and 1.8V. This also would have been nice to put
into the device tree binding. It also doesn't allow for automatically
adjusting for an external divider, commonly to measure power rails above
1.8V, e.g. the BeagleBone Black ain7 measures the 3.3V rail divided by
2.
Signed-off-by: Trent Piepho <trent.piepho@xxxxxxxxxxx>
---
drivers/aiodev/Kconfig | 8 ++
drivers/aiodev/Makefile | 1 +
drivers/aiodev/am335x_adc.c | 183 ++++++++++++++++++++++++++++++
drivers/aiodev/ti_am335x_tscadc.h | 163 ++++++++++++++++++++++++++
4 files changed, 355 insertions(+)
create mode 100644 drivers/aiodev/am335x_adc.c
create mode 100644 drivers/aiodev/ti_am335x_tscadc.h
diff --git a/drivers/aiodev/Kconfig b/drivers/aiodev/Kconfig
index a4909d8ec..5fb445c09 100644
--- a/drivers/aiodev/Kconfig
+++ b/drivers/aiodev/Kconfig
@@ -35,4 +35,12 @@ config MC13XXX_ADC
help
Support for MC13783, MC13892, MC34708 ADC
+config AM335X_ADC
+ tristate "AM335X ADC driver"
+ depends on ARCH_AM33XX
+ help
+ Support for ADC on TI AM335X SoCs. Supports simple one-shot readings
+ rather than continuous sampling with DMA, etc. ADC channels should be
+ configured via device tree, using the kernel bindings.
+
endif
diff --git a/drivers/aiodev/Makefile b/drivers/aiodev/Makefile
index d5318deeb..5f48b2022 100644
--- a/drivers/aiodev/Makefile
+++ b/drivers/aiodev/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
obj-$(CONFIG_LM75) += lm75.o
obj-$(CONFIG_MC13XXX_ADC) += mc13xxx_adc.o
obj-$(CONFIG_QORIQ_THERMAL) += qoriq_thermal.o
+obj-$(CONFIG_AM335X_ADC) += am335x_adc.o
diff --git a/drivers/aiodev/am335x_adc.c b/drivers/aiodev/am335x_adc.c
new file mode 100644
index 000000000..0d6cc426e
--- /dev/null
+++ b/drivers/aiodev/am335x_adc.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* am335x_adc.c
+ *
+ * Copyright © 2019 Synapse Product Development
+ *
+ * Author: Trent Piepho <trent.piepho@xxxxxxxxxxx>
+ *
+ * This is a simple driver for the ADC in TI's AM335x SoCs. It's designed to
+ * produce one-shot readings and doesn't use the more advanced features, like
+ * the FIFO, triggering, DMA, multi-channel scan programs, etc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <malloc.h>
+#include <driver.h>
+#include <xfuncs.h>
+#include <errno.h>
+#include <io.h>
+#include <linux/log2.h>
+#include <aiodev.h>
+#include <mach/am33xx-clock.h>
+#include "ti_am335x_tscadc.h"
+
+struct am335x_adc_data {
+ struct aiodevice aiodev;
+ void __iomem *base;
+ struct aiochannel *channels;
+};
+
+static inline void tiadc_write(const struct am335x_adc_data *data, u32 value,
+ u32 reg)
+{
+ writel(value, data->base + reg);
+}
+
+static inline u32 tiadc_read(const struct am335x_adc_data *data, u32 reg)
+{
+ return readl(data->base + reg);
+}
+
+static int am335x_adc_read(struct aiochannel *chan, int *val)
+{
+ struct am335x_adc_data *data =
+ container_of(chan->aiodev, struct am335x_adc_data, aiodev);
+ int timeout = IDLE_TIMEOUT;
+ /* This assumes VREFN = 0V and VREFP = 1.8V */
+ const u32 vrefp = 1800; /* ceil(log2(vrefp)) = 11 */
+ /* Left shift vrefp/4095 by as much as possible without overflowing 32 bits */
+ const u32 shift = 32 - (const_ilog2(vrefp) + 1);
+ const u32 factor = (vrefp << shift) / 4095u;
+ u32 counts;
+
+ /* Make sure FIFO is empty before we start, so we don't get old data */
+ while ((tiadc_read(data, REG_FIFO1CNT) & 0x7f) > 0)
+ tiadc_read(data, REG_FIFO1);
+
+ tiadc_write(data, ENB(chan->index + 1), REG_SE); /* ENB(1) is 1st channel */
+ tiadc_write(data, CNTRLREG_TSCSSENB, REG_CTRL);
+
+ while ((tiadc_read(data, REG_FIFO1CNT) & 0x7f) == 0) {
+ if (--timeout == 0)
+ return -ETIMEDOUT;
+ mdelay(1);
+ }
+
+ counts = tiadc_read(data, REG_FIFO1) & FIFOREAD_DATA_MASK;
+ *val = (counts * factor) >> shift;
+
+ tiadc_write(data, 0, REG_CTRL);
+
+ return 0;
+}
+
+static int am335x_adc_probe(struct device_d *dev)
+{
+ struct device_node *node;
+ struct am335x_adc_data *data;
+ int i, ret;
+
+ data = xzalloc(sizeof(*data));
+ data->aiodev.hwdev = dev;
+ data->aiodev.read = am335x_adc_read;
+ data->base = dev_request_mem_region(dev, 0);
+ if (IS_ERR(data->base)) {
+ ret = PTR_ERR(data->base);
+ goto fail_data;
+ }
+
+ node = of_find_compatible_node(dev->device_node, NULL, "ti,am3359-adc");
+ if (!node) {
+ ret = -EINVAL;
+ goto fail_data;
+ }
+
+ if (!of_find_property(node, "ti,adc-channels",
+ &data->aiodev.num_channels))
+ return -EINVAL;
+ data->aiodev.num_channels /= sizeof(u32);
+
+ data->channels = xzalloc(sizeof(*data->channels) *
+ data->aiodev.num_channels);
+ data->aiodev.channels = xmalloc(sizeof(*data->aiodev.channels) *
+ data->aiodev.num_channels);
+
+ /* Max ADC clock is 24 MHz or 3 MHz, depending on if one looks at the
+ * reference manual or data sheet.
+ */
+ tiadc_write(data, DIV_ROUND_UP(am33xx_get_osc_clock(), ADC_CLK) - 1,
+ REG_CLKDIV);
+ tiadc_write(data, ~0, REG_IRQCLR);
+ tiadc_write(data, ~0, REG_IRQSTATUS);
+ tiadc_write(data, 0x3, REG_DMAENABLE_CLEAR);
+ tiadc_write(data, CNTRLREG_STEPCONFIGWRT, REG_CTRL);
+ tiadc_write(data,
+ STEPCONFIG_RFP_VREFP | STEPCONFIG_RFM_VREFN |
+ STEPCONFIG_INM_ADCREFM | STEPCONFIG_INP_ADCREFM,
+ REG_IDLECONFIG);
+
+
+ for (i = 0; i < data->aiodev.num_channels; i++) {
+ u32 config, delay, ain, odelay, sdelay, avg;
+
+ data->aiodev.channels[i] = &data->channels[i];
+ data->channels[i].unit = "mV";
+ ret = of_property_read_u32_index(node, "ti,adc-channels",
+ i, &ain);
+ if (ret)
+ goto fail_channels;
+
+ ret = of_property_read_u32_index(node, "ti,chan-step-opendelay",
+ i, &odelay);
+ odelay = ret ? STEPCONFIG_OPENDLY : STEPDELAY_OPEN(odelay);
+
+ ret = of_property_read_u32_index(node, "ti,chan-step-sampledelay",
+ i, &sdelay);
+ sdelay = ret ? STEPCONFIG_SAMPLEDLY : STEPDELAY_SAMPLE(sdelay);
+
+ ret = of_property_read_u32_index(node, "ti,chan-step-avg",
+ i, &avg);
+ avg = ret ? STEPCONFIG_AVG_16 : STEPCONFIG_AVG(ilog2(avg ? : 1));
+
+ /* We program each step with one of the channels in the DT */
+ config = STEPCONFIG_RFP_VREFP | STEPCONFIG_RFM_VREFN | /* External refs */
+ /* Internal reference, use STEPCONFIG_RFP(0) | STEPCONFIG_RFM(0) */
+ STEPCONFIG_INM_ADCREFM | /* Not important, SE rather than diff */
+ STEPCONFIG_MODE(0) | STEPCONFIG_FIFO1 | /* One-shot and data to FIFO1 */
+ avg | STEPCONFIG_INP(ain);
+ delay = odelay | sdelay;
+
+ tiadc_write(data, config, REG_STEPCONFIG(i));
+ tiadc_write(data, delay, REG_STEPDELAY(i));
+ }
+ tiadc_write(data, 0, REG_CTRL);
+
+ ret = aiodevice_register(&data->aiodev);
+ if (ret)
+ goto fail_channels;
+
+ dev_info(dev, "TI AM335x ADC (%d ch) registered as %s\n",
+ data->aiodev.num_channels, dev_name(&data->aiodev.dev));
+ return 0;
+
+ fail_channels:
+ kfree(data->channels);
+ kfree(data->aiodev.channels);
+
+ fail_data:
+ kfree(data);
+ return ret;
+}
+
+static const struct of_device_id of_am335x_adc_match[] = {
+ { .compatible = "ti,am3359-tscadc", },
+ { /* end */ }
+};
+
+static struct driver_d am335x_adc_driver = {
+ .name = "am335x_adc",
+ .probe = am335x_adc_probe,
+ .of_compatible = DRV_OF_COMPAT(of_am335x_adc_match),
+};
+device_platform_driver(am335x_adc_driver);
diff --git a/drivers/aiodev/ti_am335x_tscadc.h b/drivers/aiodev/ti_am335x_tscadc.h
new file mode 100644
index 000000000..36f3c17ac
--- /dev/null
+++ b/drivers/aiodev/ti_am335x_tscadc.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
+#define __LINUX_TI_AM335X_TSCADC_MFD_H
+
+/*
+ * TI Touch Screen / ADC MFD driver
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define REG_RAWIRQSTATUS 0x024
+#define REG_IRQSTATUS 0x028
+#define REG_IRQENABLE 0x02C
+#define REG_IRQCLR 0x030
+#define REG_IRQWAKEUP 0x034
+#define REG_DMAENABLE_SET 0x038
+#define REG_DMAENABLE_CLEAR 0x03c
+#define REG_CTRL 0x040
+#define REG_ADCFSM 0x044
+#define REG_CLKDIV 0x04C
+#define REG_SE 0x054
+#define REG_IDLECONFIG 0x058
+#define REG_CHARGECONFIG 0x05C
+#define REG_CHARGEDELAY 0x060
+#define REG_STEPCONFIG(n) (0x64 + ((n) * 8))
+#define REG_STEPDELAY(n) (0x68 + ((n) * 8))
+#define REG_FIFO0CNT 0xE4
+#define REG_FIFO0THR 0xE8
+#define REG_FIFO1CNT 0xF0
+#define REG_FIFO1THR 0xF4
+#define REG_DMA1REQ 0xF8
+#define REG_FIFO0 0x100
+#define REG_FIFO1 0x200
+
+/* Register Bitfields */
+/* IRQ wakeup enable */
+#define IRQWKUP_ENB BIT(0)
+
+/* Step Enable */
+#define STEPENB_MASK (0x1FFFF << 0)
+#define STEPENB(val) ((val) << 0)
+#define ENB(val) (1 << (val))
+#define STPENB_STEPENB STEPENB(0x1FFFF)
+#define STPENB_STEPENB_TC STEPENB(0x1FFF)
+
+/* IRQ enable */
+#define IRQENB_HW_PEN BIT(0)
+#define IRQENB_EOS BIT(1)
+#define IRQENB_FIFO0THRES BIT(2)
+#define IRQENB_FIFO0OVRRUN BIT(3)
+#define IRQENB_FIFO0UNDRFLW BIT(4)
+#define IRQENB_FIFO1THRES BIT(5)
+#define IRQENB_FIFO1OVRRUN BIT(6)
+#define IRQENB_FIFO1UNDRFLW BIT(7)
+#define IRQENB_PENUP BIT(9)
+
+/* Step Configuration */
+#define STEPCONFIG_MODE_MASK (3 << 0)
+#define STEPCONFIG_MODE(val) ((val) << 0)
+#define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1)
+#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
+#define STEPCONFIG_AVG_MASK (7 << 2)
+#define STEPCONFIG_AVG(val) ((val) << 2)
+#define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
+#define STEPCONFIG_XPP BIT(5)
+#define STEPCONFIG_XNN BIT(6)
+#define STEPCONFIG_YPP BIT(7)
+#define STEPCONFIG_YNN BIT(8)
+#define STEPCONFIG_XNP BIT(9)
+#define STEPCONFIG_YPN BIT(10)
+#define STEPCONFIG_RFP(val) ((val) << 12)
+#define STEPCONFIG_RFP_VREFP (0x3 << 12)
+#define STEPCONFIG_INM_MASK (0xF << 15)
+#define STEPCONFIG_INM(val) ((val) << 15)
+#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
+#define STEPCONFIG_INP_MASK (0xF << 19)
+#define STEPCONFIG_INP(val) ((val) << 19)
+#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
+#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
+#define STEPCONFIG_FIFO1 BIT(26)
+#define STEPCONFIG_RFM(val) ((val) << 23)
+#define STEPCONFIG_RFM_VREFN (0x3 << 23)
+
+/* Delay register */
+#define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
+#define STEPDELAY_OPEN(val) ((val) << 0)
+#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
+#define STEPDELAY_SAMPLE_MASK (0xFF << 24)
+#define STEPDELAY_SAMPLE(val) ((val) << 24)
+#define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
+
+/* Charge Config */
+#define STEPCHARGE_RFP_MASK (7 << 12)
+#define STEPCHARGE_RFP(val) ((val) << 12)
+#define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
+#define STEPCHARGE_INM_MASK (0xF << 15)
+#define STEPCHARGE_INM(val) ((val) << 15)
+#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
+#define STEPCHARGE_INP_MASK (0xF << 19)
+#define STEPCHARGE_INP(val) ((val) << 19)
+#define STEPCHARGE_RFM_MASK (3 << 23)
+#define STEPCHARGE_RFM(val) ((val) << 23)
+#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
+
+/* Charge delay */
+#define CHARGEDLY_OPEN_MASK (0x3FFFF << 0)
+#define CHARGEDLY_OPEN(val) ((val) << 0)
+#define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(0x400)
+
+/* Control register */
+#define CNTRLREG_TSCSSENB BIT(0)
+#define CNTRLREG_STEPID BIT(1)
+#define CNTRLREG_STEPCONFIGWRT BIT(2)
+#define CNTRLREG_POWERDOWN BIT(4)
+#define CNTRLREG_AFE_CTRL_MASK (3 << 5)
+#define CNTRLREG_AFE_CTRL(val) ((val) << 5)
+#define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1)
+#define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2)
+#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
+#define CNTRLREG_TSCENB BIT(7)
+
+/* FIFO READ Register */
+#define FIFOREAD_DATA_BITS 12
+#define FIFOREAD_DATA_MASK (BIT(FIFOREAD_DATA_BITS) - 1)
+#define FIFOREAD_CHNLID_MASK (0xf << 16)
+
+/* DMA ENABLE/CLEAR Register */
+#define DMA_FIFO0 BIT(0)
+#define DMA_FIFO1 BIT(1)
+
+/* Sequencer Status */
+#define SEQ_STATUS BIT(5)
+#define CHARGE_STEP 0x11
+
+#define ADC_CLK 3000000
+#define TOTAL_STEPS 16
+#define TOTAL_CHANNELS 8
+#define FIFO1_THRESHOLD 19
+
+/*
+ * time in us for processing a single channel, calculated as follows:
+ *
+ * max num cycles = open delay + (sample delay + conv time) * averaging
+ *
+ * max num cycles: 262143 + (255 + 13) * 16 = 266431
+ *
+ * clock frequency: 26MHz / 8 = 3.25MHz
+ * clock period: 1 / 3.25MHz = 308ns
+ *
+ * max processing time: 266431 * 308ns = 83ms(approx)
+ */
+#define IDLE_TIMEOUT 83 /* milliseconds */
+
+#endif
--
2.26.2
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