Hi Marco, On Thu, Aug 06, 2020 at 11:29:19AM +0200, Marco Felsch wrote: > Setup the ENET TX reference clk to get it from the internal clock from > anatop. This is the default value for newer imx6 processors like: 6sx, > 6ul, 6ull. So it should be safe to set it as default for imx6q/d too. I don't follow this reasoning. We only ever know the boards that are unhappy with the reset default, because these are the ones that change it. Now if we change the register default we can't know which boards stop working because they relied on the previous reset default value. Here is an example from U-Boot where this bit is explicitly cleared: board/tqc/tqma6/tqma6_mba6.c:85: clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); We support this board in barebox as well and it might break with your change, so I don't think this patch is a good idea. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
