The commit is based on linux commit:
8<-----------------------------------------------------------
commit 9f55eb92441883a1afca48dc8d32bf62c4d8e833
Author: Fugang Duan <b38611@xxxxxxxxxxxxx>
Date: Tue Jul 28 15:30:39 2015 +0800
ARM: imx6ul: add fec bits to GPR syscon definition
FEC requires additional bits to select refrence clock.
Signed-off-by: Fugang Duan <B38611@xxxxxxxxxxxxx>
Signed-off-by: Shawn Guo <shawnguo@xxxxxxxxxx>
8<-----------------------------------------------------------
Signed-off-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
---
include/mfd/imx6q-iomuxc-gpr.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/mfd/imx6q-iomuxc-gpr.h b/include/mfd/imx6q-iomuxc-gpr.h
index b2c9da6579..16c83a778c 100644
--- a/include/mfd/imx6q-iomuxc-gpr.h
+++ b/include/mfd/imx6q-iomuxc-gpr.h
@@ -344,4 +344,12 @@
#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
+/* For imx6ul iomux gpr register field define */
+#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18)
+#define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18)
+#define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17)
+#define IMX6UL_GPR1_ENET_CLK_OUTPUT (0x3 << 17)
+
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
--
2.20.1
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