Hi Fabio, thank you for your quick reply. I've already found the errata you linked in your mail but I had no success applying the suggestion there; maybe I'm doing it wrong. Let's take the Option 3 there: Use the SNVS LPCR register to turn off the system power It suggests to set the SNVS_LPCR[TOP] bit together with SNVS_LPCR[DP_EN], this would mean something like: # mw -l 0x30370038 0x00000060 But the effect of this write is to hang the soc. The same happens with the Option 2 in the errata: Use SRC_A7RCR0[A7_CORE_POR_RESET0] to reset the ARM A7. To do this I use: # mw -l 0x30390004 0x00000003 but again the soc just hangs as with the watchdog. giorgio > On June 23, 2020 at 3:53 PM Fabio Estevam <festevam@xxxxxxxxx> wrote: > > > Hi Giorgio, > > On Tue, Jun 23, 2020 at 10:48 AM Giorgio Dal Molin > <giorgio.nicole@xxxxxxxx> wrote: > > > Can anyone confirm that the current barebox is able to restart an imx7 soc without > > using external signals ? > > You really need to use the WDOG_B pin to trigger the reset due to an > i.MX7 erratum. > > Please check the i.MX7 errata document: > https://www.nxp.com/docs/en/errata/IMX7DS_3N09P.pdf > > Search for "e10574 Watchdog: A watchdog timeout or software trigger > will not reset the SOC" > > _______________________________________________ > barebox mailing list > barebox@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/barebox _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
