[PATCH 18/21] clk: at91: allow 24 Mhz clock as input for PLL

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From: Eugen Hristev <eugen.hristev@xxxxxxxxxxxxx>

The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct

Signed-off-by: Eugen Hristev <eugen.hristev@xxxxxxxxxxxxx>
Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@xxxxxxxxxxxxx
Acked-by: Nicolas Ferre <nicolas.ferre@xxxxxxxxxxxxx>
Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
[afa: ported to barebox from Linux commit 81a6b601f9f49]
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
 drivers/clk/at91/sama5d2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 3daff89f5958..61fdf256c036 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -27,7 +27,7 @@ static const struct clk_range plla_outputs[] = {
 };
 
 static const struct clk_pll_characteristics plla_characteristics = {
-	.input = { .min = 12000000, .max = 12000000 },
+	.input = { .min = 12000000, .max = 24000000 },
 	.num_output = ARRAY_SIZE(plla_outputs),
 	.output = plla_outputs,
 	.icpll = plla_icpll,
-- 
2.26.0.rc2


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