Hi Michael, Am Donnerstag, den 19.03.2020, 10:38 +0000 schrieb Michael Graichen: > Hey, > > i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC. > I have seen that Barebox has an defconfig for the zynq > so i tried > > export ARCH=arm > export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf- > export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH > make zynq_defconfig > make -j`nproc` > > which compiles me the image > > barebox-flash-image -> images/barebox-avnet-zedboard.img > > when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool > > dev$ bootgen -image bootimage.bif -o i BOOT.bin > > and .bif file was > > dev$ cat bootimage.bif > //arch = zynq; split = false; format = BIN > the_ROM_image: > { > [bootloader]FSBL.elf > design_1_wrapper.bit > u-boot.elf > } > > > that i copied onto an SD-Card and powed up the board. > > But since i want to use Barebox how do i produce the BOOT.bin file? The barebox-avnet-zedboard.img already is the BOOT.bin image, just copy it to the SD card with this name and you are done. > and how is the programming of the FPGA Logic done? Barebox currently doesn't support loading the FPGA bitstream. We are still lacking a driver for the DevC PCAP interface. Zynq support in Barebox is only a spare time (and thus toy) project at this time. It works okay for booting Linux on the PS part of the system, but almost fully lacks support for the PL part. That said I wouldn't mind helping with getting the missing bits added by reviewing/testing patches. :) Regards, Lucas _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
