On Wed, Feb 19, 2020 at 07:23:09AM +0100, Oleksij Rempel wrote: > Am 18.02.20 um 16:37 schrieb Sascha Hauer: > > It seems running from the NFC SRAM doesn't work with the instruction > > cache enabled, it leads to corruptions on the i.MX27. We stumbled upon > > this earlier and the solution at that time was to disable the > > instruction cache in the NAND boot code. It is, however, more reliable > > to just not enable the instruction cache in the first place. > > This is not particularly nice as we have to ifdef this in generic code, > > duplicate arm_cpu_lowlevel_init(), or call arm_cpu_lowlevel_init() later > > when we are out of NFC SRAM. From the different bad solutions I chose > > to ifdef the instruction cache away. It will be enabled later in the > > common cache functions. > > > Hm... is it possible that we have similar speculation issues as on i.MX6UL? The CPU was speculating > in to IOMEM, caused cache poisoning/corruption and executed corrupted cache. I don't know how much speculation an ARM9 processor does, but the end result looks very similar. via JTAG I can see that the memory matches my disassembly, just the CPU does something completely different. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
