There's new infrastructure for runtime determining RAM size. Use it so
we don't need to hard code it in PBL and board code.
Because this new infrastructure has some nested function calls, my
arm-v7a-linux-gnueabihf-gcc 9.2.1 (OSELAS.Toolchain-2019.09.0)
spills to the stack. Add stm32mp_cpu_lowlevel_init, which also sets up
a stack after barebox end so this works.
Lastly, there's no upstream device tree node for the DDR controller.
Add one in the barebox device tree, so we don't have to hardcode the
DDRCTRL address into non-pbl code that's run everywhere.
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
arch/arm/boards/stm32mp157c-dk2/board.c | 11 -----------
arch/arm/boards/stm32mp157c-dk2/lowlevel.c | 8 +++-----
arch/arm/dts/stm32mp157c.dtsi | 7 +++++++
3 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c
index f15ae0b4aff0..9cd5b4ee1ff4 100644
--- a/arch/arm/boards/stm32mp157c-dk2/board.c
+++ b/arch/arm/boards/stm32mp157c-dk2/board.c
@@ -6,17 +6,6 @@
#include <mach/stm32.h>
#include <mach/bbu.h>
-static int dk2_mem_init(void)
-{
- if (!of_machine_is_compatible("st,stm32mp157c-dk2"))
- return 0;
-
- arm_add_mem_device("ram0", STM32_DDR_BASE, SZ_512M);
-
- return 0;
-}
-mem_initcall(dk2_mem_init);
-
static int dk2_postcore_init(void)
{
if (!of_machine_is_compatible("st,stm32mp157c-dk2"))
diff --git a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c
index 2106eaadc93a..7261d7a8bc58 100644
--- a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c
+++ b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c
@@ -1,8 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
-#include <mach/stm32.h>
+#include <mach/entry.h>
#include <debug_ll.h>
extern char __dtb_z_stm32mp157c_dk2_start[];
@@ -17,12 +15,12 @@ ENTRY_FUNCTION(start_stm32mp157c_dk2, r0, r1, r2)
{
void *fdt;
- arm_cpu_lowlevel_init();
+ stm32mp_cpu_lowlevel_init();
if (IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
fdt = __dtb_z_stm32mp157c_dk2_start + get_runtime_offset();
- barebox_arm_entry(STM32_DDR_BASE, SZ_512M, fdt);
+ stm32mp1_barebox_entry(fdt);
}
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index decb4ab6d5c4..bd2aabe6343a 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -24,6 +24,13 @@
psci {
compatible = "arm,psci-0.2";
};
+
+ soc {
+ memory-controller@5a003000 {
+ compatible = "st,stm32-ddrctrl";
+ reg = <0x5a003000 0x1000>;
+ };
+ };
};
&bsec {
--
2.24.0.rc1
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