On Thu, Oct 17, 2019 at 12:40:39PM +0200, Steffen Trumtrar wrote: > Barebox-version of the Linux v5.2 patch: > > 40ae25505fe834648ce4aa70b073ee934942bfdb > net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10 > > On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from > the Cyclone5 and Arria5: > - The emac PHY setup bits are in separate registers. > - The PTP reference clock select mask is different. > - The register to enable the emac signal from FPGA is different. > > Thus, this patch creates a separate function for setting the phy modes on > Arria10/Agilex/Stratix10. The separation is based a new DTS binding: > "altr,socfpga-stmmac-a10-s10". > > Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx> > Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx> > > The new DTS binding is already part of v2019.10.0 and the driver doesn't > probe on Arria10 without the new binding introduced in this patch. > > Signed-off-by: Steffen Trumtrar <s.trumtrar@xxxxxxxxxxxxxx> > --- > drivers/net/designware.h | 1 + > drivers/net/designware_socfpga.c | 133 +++++++++++++++++++++++++++---- > 2 files changed, 118 insertions(+), 16 deletions(-) Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
