[PATCH v2] MIPS: init cache before using it

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flush_cache_all() uses 'struct cpuinfo_mips current_cpu_data' data
fields. These data fields are initialized in r4k_cache_init().

However in the current implementation the r4k_cache_init() function
is called __AFTER__ relocate_code().

Suggested-by: Antony Pavlov <antonynpavlov@xxxxxxxxx>
Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
---
 arch/mips/lib/reloc.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
index 9a9e404f7e..14195d6f96 100644
--- a/arch/mips/lib/reloc.c
+++ b/arch/mips/lib/reloc.c
@@ -31,6 +31,7 @@
 #include <asm/bitops.h>
 #include <asm/cache.h>
 #include <asm/cacheops.h>
+#include <asm/cpu-features.h>
 #include <asm/cpu.h>
 #include <asm/cpu-info.h>
 #include <asm/io.h>
@@ -40,6 +41,7 @@
 #include <linux/sizes.h>
 #include <asm-generic/memory_layout.h>
 
+extern void r4k_cache_init(void);
 void main_entry(void *fdt, u32 fdt_size);
 void relocate_code(void *fdt, u32 fdt_size, u32 relocaddr);
 
@@ -146,8 +148,14 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
 		apply_reloc(type, (void *)addr, off);
 	}
 
-	/* Ensure the icache is coherent */
-	flush_cache_all();
+	memset(__bss_start, 0, bss_len);
+
+	cpu_probe();
+	if (cpu_has_4k_cache) {
+		r4k_cache_init();
+		/* Ensure the icache is coherent */
+		flush_cache_all();
+	}
 
 	/* Clear the .bss section */
 	bss_start = (uint8_t *)((unsigned long)__bss_start + off);
-- 
2.23.0


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