On Tue, Oct 15, 2019 at 11:41:06PM +0300, Antony Pavlov wrote: > On Tue, 15 Oct 2019 18:09:45 +0200 > Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx> wrote: > > Hi! > > Please review this thread http://lists.infradead.org/pipermail/barebox/2019-June/038530.html > AFAIR we have to clear BSS before calling r4k_cache_init(). Hm... your patch need some rework as well. I'll send updated version. > -- > Best regards, > Antony Pavlov > > > Cache information was not initialized on flush_cache_all(). This was the > > reason for relatively slow boot speed on MIPS. > > > > Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx> > > --- > > arch/mips/lib/reloc.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c > > index 9a9e404f7e..3d05ff1381 100644 > > --- a/arch/mips/lib/reloc.c > > +++ b/arch/mips/lib/reloc.c > > @@ -40,6 +40,7 @@ > > #include <linux/sizes.h> > > #include <asm-generic/memory_layout.h> > > > > +void r4k_cache_init(void); > > void main_entry(void *fdt, u32 fdt_size); > > void relocate_code(void *fdt, u32 fdt_size, u32 relocaddr); > > > > @@ -146,6 +147,7 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size) > > apply_reloc(type, (void *)addr, off); > > } > > > > + r4k_cache_init(); > > /* Ensure the icache is coherent */ > > flush_cache_all(); > > > > -- > > 2.23.0 > > > > > > _______________________________________________ > > barebox mailing list > > barebox@xxxxxxxxxxxxxxxxxxx > > http://lists.infradead.org/mailman/listinfo/barebox > > _______________________________________________ > barebox mailing list > barebox@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/barebox > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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