From: Ahmad Fatoum <ahmad@xxxxxx> With barebox using the manager permissions for domain 0 that's used for all page table entries and directories, we never had the need so far to explicitly set R/W bits. We did so anyway for sections in the early MMU code, but later on in the normal MMU setup, we didn't do so consistently. In preparation for switching to DOMAIN_CLIENT for ARMv7, configure R/W everywhere in normal MMU code as well. Signed-off-by: Ahmad Fatoum <ahmad@xxxxxx> --- arch/arm/cpu/mmu.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index 123e19e9e55c..f7158871fe6f 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -56,13 +56,14 @@ static inline void tlb_invalidate(void) ); } -#define PTE_FLAGS_CACHED_V7 (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE) -#define PTE_FLAGS_WC_V7 (PTE_EXT_TEX(1) | PTE_EXT_XN) -#define PTE_FLAGS_UNCACHED_V7 PTE_EXT_XN +#define PTE_FLAGS_CACHED_V7 (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE | \ + PTE_EXT_AP_URW_SRW) +#define PTE_FLAGS_WC_V7 (PTE_EXT_TEX(1) | PTE_EXT_AP_URW_SRW | PTE_EXT_XN) +#define PTE_FLAGS_UNCACHED_V7 (PTE_EXT_AP_URW_SRW | PTE_EXT_XN) #define PTE_FLAGS_CACHED_V4 (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE) #define PTE_FLAGS_UNCACHED_V4 PTE_SMALL_AP_UNO_SRW -#define PGD_FLAGS_WC_V7 (PMD_SECT_TEX(1) | PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ - PMD_SECT_XN) +#define PGD_FLAGS_WC_V7 (PMD_SECT_TEX(1) | PMD_SECT_DEF_UNCACHED | \ + PMD_SECT_BUFFERABLE | PMD_SECT_XN) #define PGD_FLAGS_UNCACHED_V7 (PMD_SECT_DEF_UNCACHED | PMD_SECT_XN) /* -- 2.23.0 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
