Hello Ahmad,
with these two patches applied, the NXP i.MX8MQ no longer starts into
barebox.
- rcz
On Tue, 2019-10-01 at 11:09 +0200, Ahmad Fatoum wrote:
> So far arm_early_mmu_cache_flush has only been used in preparation
> for
> executing newly-written code. For this reason, on ARMv7 and below,
> it had always invalidate the icache after the dcache flush.
> We don't do this on ARM64, but sync_caches_for_execution depends on
> this,
> which had this comment that didn't hold true for ARM64:
>
> > Despite the name arm_early_mmu_cache_flush not only flushes the
> > data cache, but also invalidates the instruction cache.
>
> It might be worthwhile to decouple dcache flushing from icache
> invalidation, but for now, align what we do on ARM64 with what we do
> for
> 32-bit ARMs.
>
> This fixes a potential read of stale instructions when loading
> second-stage barebox from the PBL with MMU disabled.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
> ---
> arch/arm/cpu/cache_64.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/cpu/cache_64.c b/arch/arm/cpu/cache_64.c
> index 45f01e8dc9cf..847323525424 100644
> --- a/arch/arm/cpu/cache_64.c
> +++ b/arch/arm/cpu/cache_64.c
> @@ -27,6 +27,7 @@ int arm_set_cache_functions(void)
> void arm_early_mmu_cache_flush(void)
> {
> v8_flush_dcache_all();
> + v8_invalidate_icache_all();
> }
>
> void arm_early_mmu_cache_invalidate(void)
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