On some ARM cores, cache contents are indeterminate after a Power-On
Reset. Turning on the MMU on such cores risks interpreting random cache
lines as valid, causing hard-to-debug errors.
For this reason, we always invalidate the dcache on <= ARMv7. Let's do
likewise for ARM64. Newer ARM cores tend to come up with their dcaches
invalidated already, but for some, like the Cortex-A72, L2 caches are
invalidated dependent on a signal sampled at reset, so better play
it safe.
The icache invalidate here seems to serve no useful purpose. It's kept
for now for symmetry with ARM32.
Note that this is wrong should barebox be entered with the MMU enabled,
but this is so far not the case with any ARM64 platform we support.
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
arch/arm/cpu/cache_64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/cache_64.c b/arch/arm/cpu/cache_64.c
index 847323525424..6e18d981a434 100644
--- a/arch/arm/cpu/cache_64.c
+++ b/arch/arm/cpu/cache_64.c
@@ -32,5 +32,6 @@ void arm_early_mmu_cache_flush(void)
void arm_early_mmu_cache_invalidate(void)
{
+ v8_invalidate_dcache_all();
v8_invalidate_icache_all();
}
--
2.23.0
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