Hi Ahmad, On Wed, Jul 17, 2019 at 07:06:03PM +0200, Ahmad Fatoum wrote: > From: Fabio Estevam <fabio.estevam@xxxxxxx> > > Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk > tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to > enter the ldb_di_ipu_div divider. If the divider gets locked up, no > ldb_di[x]_clk is generated, and the LVDS display will hang when the > ipu_di_clk is sourced from ldb_di_clk. I haven't investigates any further, but this one breaks NAND support at least on my phyCORE i.MX6 board. With this patch applied we get: MXS: Timeout resetting block via register 0x00112000 mxs_nand 112000.gpmi-nand@xxxxxxxxx: probe failed: Connection timed out Does this patch disable any clocks necessary for NAND? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
