((x & (1 << 10)) == 0x1) can never be true as the compiler mourns about. Fix this to actually do what the comment says: Wait till bit 10 is cleared. Looking at the corresponding U-Boot code also suggests that this is the right thing to do. Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- arch/arm/mach-omap/am35xx_emif4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c index 38fc0f02d2..678a338fd6 100644 --- a/arch/arm/mach-omap/am35xx_emif4.c +++ b/arch/arm/mach-omap/am35xx_emif4.c @@ -37,7 +37,7 @@ void am35xx_emif4_init(void) writel(regval, &emif4_base->sdram_iodft_tlgc); /* Wait till that bit clears*/ - while ((readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)) == 0x1); + while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)); /* Re-verify the DDR PHY status*/ while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0); -- 2.23.0 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
