As observed on CFU1 board, without this delay we interrupt mask ROM
code execution even before it sets up any PLLs correctly preventing
Barebox from correctly starting up. Fixing this by adding PLL setup
code to OpenOCD script helps somewhat and Barebox starts, howerver CPU
started this way ends up being unstable crashing randomly during
further Barebox use.
Adding a simple 100 ms post reset delay resolves all of the described
issues. This is also consistent with how other ZII boards are set up.
Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
---
Documentation/boards/imx/zii-vf610-dev/openocd.cfg | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/boards/imx/zii-vf610-dev/openocd.cfg b/Documentation/boards/imx/zii-vf610-dev/openocd.cfg
index 509f9e33c..0d0e0d578 100644
--- a/Documentation/boards/imx/zii-vf610-dev/openocd.cfg
+++ b/Documentation/boards/imx/zii-vf610-dev/openocd.cfg
@@ -19,6 +19,8 @@ reset_config srst_only srst_push_pull connect_deassert_srst
# set a slow default JTAG clock, can be overridden later
adapter_khz 1000
+adapter_nsrst_delay 100
+
# Source generic VF6xx target configuration
source [find target/vybrid_vf6xx.cfg]
source [find mem_helper.tcl]
@@ -186,8 +188,7 @@ proc clock_init { } {
#
# This code assumes that debugger would be unable to prevent
# MaskROM initialization code from running before halting the
- # processor. TODO: Port the initial clock settings as
- # specified in TRM
+ # processor.
#
# Ungate all of the peripheral clocks
#
--
2.21.0
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