Incoming PSCI implementation for the STM32MP1 needs
to get_gicd_base_address as well, so move it to gic.h to
avoid code duplication.
Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
---
arch/arm/cpu/sm.c | 29 +----------------------------
arch/arm/include/asm/gic.h | 29 +++++++++++++++++++++++++++++
2 files changed, 30 insertions(+), 28 deletions(-)
diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c
index d9d62fbd9db0..b7a9eae89b1a 100644
--- a/arch/arm/cpu/sm.c
+++ b/arch/arm/cpu/sm.c
@@ -22,9 +22,6 @@
#include "mmu.h"
-/* valid bits in CBAR register / PERIPHBASE value */
-#define CBAR_MASK 0xFFFF8000
-
static unsigned int read_id_pfr1(void)
{
unsigned int reg;
@@ -51,30 +48,6 @@ static void write_mvbar(u32 val)
asm("mcr p15, 0, %0, c12, c0, 1" : : "r"(val));
}
-static unsigned long get_cbar(void)
-{
- unsigned periphbase;
-
- /* get the GIC base address from the CBAR register */
- asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
-
- /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
- * encode this). Bail out here since we cannot access this without
- * enabling paging.
- */
- if ((periphbase & 0xff) != 0) {
- pr_err("PERIPHBASE is above 4 GB, no access.\n");
- return -1;
- }
-
- return periphbase & CBAR_MASK;
-}
-
-static unsigned long get_gicd_base_address(void)
-{
- return get_cbar() + GIC_DIST_OFFSET;
-}
-
static int cpu_is_virt_capable(void)
{
return read_id_pfr1() & (1 << 12);
@@ -267,4 +240,4 @@ static int sm_init(void)
return 0;
}
-device_initcall(sm_init);
\ No newline at end of file
+device_initcall(sm_init);
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index bd3a80cdf70a..f83f52814107 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -107,4 +107,33 @@
#define ICC_SGI1R_EL1 S3_0_C12_C11_5
#define ICC_ASGI1R_EL1 S3_0_C12_C11_6
+#ifndef __ASSEMBLY__
+/* valid bits in CBAR register / PERIPHBASE value */
+#define CBAR_MASK 0xFFFF8000
+
+static inline unsigned long get_cbar(void)
+{
+ unsigned periphbase;
+
+ /* get the GIC base address from the CBAR register */
+ asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
+
+ /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
+ * encode this). Bail out here since we cannot access this without
+ * enabling paging.
+ */
+ if ((periphbase & 0xff) != 0) {
+ pr_err("PERIPHBASE is above 4 GB, no access.\n");
+ return -1;
+ }
+
+ return periphbase & CBAR_MASK;
+}
+
+static inline unsigned long get_gicd_base_address(void)
+{
+ return get_cbar() + GIC_DIST_OFFSET;
+}
+#endif
+
#endif /* __GIC_H__ */
--
2.20.1
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