On Tue, Apr 23, 2019 at 11:32:48PM -0700, Andrey Smirnov wrote: > There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3, > SCTLR will be in a state we expect it to be. Add code to reset it to a > known state, so we'd always start form clean slate. This is also > matches what we've been doing non 64-bit ARMs. > > Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon > appear to have different mask ROM behaviour where it now leaves MMU > enabled if no valid boot source is found. Page table it sets up > doesn't include DDR range, so trying to bootstrap the device via > JTAG/OpenOCD results in an abort. > > The value for SCTLR_ELx_FLAGS was taken from Linux kernel. > > Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx> > --- > arch/arm/cpu/lowlevel_64.S | 7 +++++++ > arch/arm/include/asm/system.h | 20 ++++++++++++++++++++ > 2 files changed, 27 insertions(+) Applied, thanks Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
