Hello Sam, On 23/4/19 19:39, Sam Ravnborg wrote: > Hi Ahmad. > > On Tue, Apr 23, 2019 at 07:18:48PM +0200, Ahmad Fatoum wrote: >> The v7 ARM states that all cache and branch predictor maintenance operations >> that do not specify an address execute, relative to each other, in program >> order. However, because of this erratum, an L2 set/way cache maintenance >> operation can overtake an L1 set/way cache maintenance operation, this would >> cause the data corruption. >> >> This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. >> >> This patch is the SW workaround by adding a DSB before changing cache levels as >> the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation. >> >> Signed-off-by: Jason Liu <r64343@xxxxxxxxxxxxx> >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@xxxxxxxxxx> >> Acked-by: Arnd Bergmann <arnd@xxxxxxxx> >> [afa: picked from LKML: <20190214083145.15148-1-benjamin.gaignard@xxxxxxxxxx>] >> [afa: edited commit message headline] >> Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx> >> --- >> arch/arm/Kconfig | 12 ++++++++++++ >> arch/arm/cpu/cache-armv7.S | 3 +++ >> 2 files changed, 15 insertions(+) >> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >> index a683c9c86661..fc622640aa2b 100644 >> --- a/arch/arm/Kconfig >> +++ b/arch/arm/Kconfig >> @@ -448,4 +448,16 @@ config ARM_PSCI_DEBUG >> putc function. >> Only use for debugging. >> >> +config ARM_ERRATA_814220 >> + bool "ARM errata: Cache maintenance by set/way operations can execute out of order" >> + depends on CPU_V7 >> + help >> + The v7 ARM states that all cache and branch predictor maintenance >> + operations that do not specify an address execute, relative to >> + each other, in program order. > I have a hard time parsing the above. Seems like the last part of the > sentence is maybe missing? The [..] [manual] states that [..] operations [..] execute [..] in program order. > >> + However, because of this erratum, an L2 set/way cache maintenance >> + operation can overtake an L1 set/way cache maintenance operation. >> + This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, >> + r0p4, r0p5. > It would be good to say that this should be enabled if so-and-so. > > also consider the cost to have it always enabled. It is a single asm > instruction but I do not know the impact on a typical boot. I don't know either, but as there are two in favor of doing away with the Kconfig option, I'll do so in v2. Cheers Ahmad > > Sam > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
