On Wed, Mar 06, 2019 at 11:48:13PM -0800, Andrey Smirnov wrote:
> Toggle GCTL.CORESOFTRESET before trying to access any of the block's
> registers. Without this additional step, first read of DWC3_GHWPARAMS*
> that follows results in assertion of GSTS.CSRTIMEOUT and IP block
> stuck in a non-functional state.
>
> Note that all above has only been observed on i.MX8MQ (ZII Zest board)
> for USB1 controller. USB2 doesn't seem to be affected by this.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
> ---
> drivers/usb/dwc3/core.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 2e7031a34..1fc24a441 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -663,6 +663,21 @@ static void dwc3_check_params(struct dwc3 *dwc)
> }
> }
>
> +static void dwc3_coresoft_reset(struct dwc3 *dwc)
> +{
> + u32 reg;
> +
> + reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> + reg |= DWC3_GCTL_CORESOFTRESET;
> + dwc3_writel(dwc->regs, DWC3_GCTL, reg);
> +
> + mdelay(100);
100ms is quite long. Isn't a shorter delay enough?
Sascha
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