On Thu, 3 Jan 2019 12:18:09 +0100 Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> wrote: > On Tue, Dec 18, 2018 at 10:19:33AM +0300, Antony Pavlov wrote: > > This patchseries adds initial RISC-V architecture support for barebox. > > It's very nice to get RISC-V support for barebox. > > The code looks fine from a first glance. I would prefer using multi > image support from the start of course, but I think I can live without > it. > I do not have the bandwidth to look at the code so closely to give any > valuable input though. I am fine to apply it if you want to, or you > could continue to develop it out of tree if that's more convenient for > you. Your choice. Hi Sascha! Please apply RISC-V patchseries. It's looks like people need a good bootloader for RISC-V ;) E.g.: https://www.mail-archive.com/coreboot@xxxxxxxxxxxx/msg52977.html https://forums.sifive.com/t/coreboot-or-u-boot/1186 I'm planning to add linux-capable 64-bit SiFive Unleashed board support in the next RISC-V patchseries. See https://www.sifive.com/boards/hifive-unleashed for details. At least current qemu supports Unleashed-class boards. -- Best regards, Antony Pavlov _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
