[PATCH v2 30/65] PCI: designware: Uninline register accessors

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Port of a Linux commit 3d469939bcdf044d9f370be4f6bf21436afea310

  The register accessors are not performance critical and small enough that
  the compiler can inline them itself if it makes sense.

  Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>

Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
---
 drivers/pci/pcie-designware.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index e01621d03..3aa048779 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -158,14 +158,14 @@ void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)
 		writel(val, pp->dbi_base + reg);
 }
 
-static inline u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg)
+static u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg)
 {
 	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
 
 	return dw_pcie_readl_rc(pp, offset + reg);
 }
 
-static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index,
+static void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index,
 					u32 val, u32 reg)
 {
 	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
-- 
2.19.1


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