[PATCH v2 22/65] PCI: designware: Check LTSSM training bit before deciding link is up

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Port of a Linux commit 01c076732e8288485c22ef50f20949455a783ca9

  The link may be up but still in link training.  In this case, we can't
  think the link is up and operating correctly.  Teach dw_pcie_link_up() to
  be aware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.

  Also rewrite PCIE_PHY_DEBUG_R1_LINK_UP definition so that it's consistent
  with other macros.

  Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxxx>
  Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
  Acked-by: Joao Pinto <jpinto@xxxxxxxxxxxx>

Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
---
 drivers/pci/pcie-designware.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index 5d0f782f4..a6006201e 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -98,7 +98,8 @@
 /* PCIe Port Logic registers */
 #define PLR_OFFSET                     0x700
 #define PCIE_PHY_DEBUG_R1              (PLR_OFFSET + 0x2c)
-#define PCIE_PHY_DEBUG_R1_LINK_UP      0x00000010
+#define PCIE_PHY_DEBUG_R1_LINK_UP      (0x1 << 4)
+#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING     (0x1 << 29)
 
 static unsigned long global_io_offset;
 
@@ -279,7 +280,8 @@ int dw_pcie_link_up(struct pcie_port *pp)
 		return pp->ops->link_up(pp);
 
 	val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
-	return val & PCIE_PHY_DEBUG_R1_LINK_UP;
+	return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
+		!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING));
 }
 
 static inline struct pcie_port *host_to_pcie(struct pci_controller *host)
-- 
2.19.1


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