[PATCH v2 04/65] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK

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Port of a Linux commit ed8b472df44af6dc4cb18e828dc9bb2d57f14b9e

  The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8.  In IP
  v4.2, bits [16:8] are defined for NUM_OF_LANES.  But in IP v4.4, bits[12:8]
  are defined for NUM_OF_LANES, bits [16:13] are for other usages (bit 16 is
  AUTO_LANE_FLIP_CTRL_EN, bits [15:13] are PRE_DET_LANE).

  As there is no conflict about NUM_OF_LANES between v4.2 and v4.4, change
  the mask value to avoid future problems.

  Signed-off-by: Zhou Wang <wangzhou1@xxxxxxxxxxxxx>
  Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
  Acked-by: Jingoo Han <jingoohan1@xxxxxxxxx>

Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
---
 drivers/pci/pcie-designware.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index 1ef544c7b..547d402a7 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -39,7 +39,7 @@
 
 #define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
 #define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1ff << 8)
+#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1f << 8)
 #define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
 #define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
 #define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)
-- 
2.19.1


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