[PATCH 10/58] PCI: designware: Simplify control flow

[Andrey Smirnov <andrew.smirnov@xxxxxxxxx>]

Port of a Linux commit 116a489d78b30862a2dd04961d3ba98fe4704220

  Return values immediately when possible to simplify the control flow.

  No functional change intended.  Folded in unused variable removal as
  pointed out by Fabio Estevam <fabio.estevam@xxxxxxx>, Arnd Bergmann
  <arnd@xxxxxxxx>, and Thierry Reding <thierry.reding@xxxxxxxxx>.

  Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
  Acked-by: Pratyush Anand <pratyush.anand@xxxxxxxxx>

Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
---
 drivers/pci/pcie-designware.c | 53 ++++++++++++++---------------------
 1 file changed, 21 insertions(+), 32 deletions(-)

diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index f52b67f4f..782da2626 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -133,29 +133,19 @@ static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
 			       u32 *val)
 {
-	int ret;
-
 	if (pp->ops->rd_own_conf)
-		ret = pp->ops->rd_own_conf(pp, where, size, val);
-	else
-		ret = dw_pcie_cfg_read(pp->dbi_base + where,
-				       size, val);
+		return pp->ops->rd_own_conf(pp, where, size, val);
 
-	return ret;
+	return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
 }
 
 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 			       u32 val)
 {
-	int ret;
-
 	if (pp->ops->wr_own_conf)
-		ret = pp->ops->wr_own_conf(pp, where, size, val);
-	else
-		ret = dw_pcie_cfg_write(pp->dbi_base + where,
-					size, val);
+		return pp->ops->wr_own_conf(pp, where, size, val);
 
-	return ret;
+	return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
 }
 
 static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
@@ -185,8 +175,8 @@ int dw_pcie_link_up(struct pcie_port *pp)
 {
 	if (pp->ops->link_up)
 		return pp->ops->link_up(pp);
-	else
-		return 0;
+
+	return 0;
 }
 
 static inline struct pcie_port *host_to_pcie(struct pci_controller *host)
@@ -430,16 +420,16 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 
 	data_abort_mask();
 
-	if (bus->number != pp->root_bus_nr)
-		if (pp->ops->rd_other_conf)
-			ret = pp->ops->rd_other_conf(pp, bus, devfn,
-						where, size, val);
-		else
-			ret = dw_pcie_rd_other_conf(pp, bus, devfn,
-						where, size, val);
-	else
+	if (bus->number == pp->root_bus_nr)
 		ret = dw_pcie_rd_own_conf(pp, where, size, val);
 
+	else if (pp->ops->rd_other_conf)
+		ret = pp->ops->rd_other_conf(pp, bus, devfn,
+					     where, size, val);
+	else
+		ret = dw_pcie_rd_other_conf(pp, bus, devfn,
+					    where, size, val);
+
 	if (data_abort_unmask())
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
@@ -457,15 +447,14 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 
 	data_abort_mask();
 
-	if (bus->number != pp->root_bus_nr)
-		if (pp->ops->wr_other_conf)
-			ret = pp->ops->wr_other_conf(pp, bus, devfn,
-						where, size, val);
-		else
-			ret = dw_pcie_wr_other_conf(pp, bus, devfn,
-						where, size, val);
-	else
+	if (bus->number == pp->root_bus_nr)
 		ret = dw_pcie_wr_own_conf(pp, where, size, val);
+	else if (pp->ops->wr_other_conf)
+		ret = pp->ops->wr_other_conf(pp, bus, devfn,
+					     where, size, val);
+	else
+		ret = dw_pcie_wr_other_conf(pp, bus, devfn,
+					    where, size, val);
 
 	if (data_abort_unmask())
 		return PCIBIOS_DEVICE_NOT_FOUND;
-- 
2.19.1


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