On 11/15/18 9:02 AM, Sascha Hauer wrote: > On Wed, Nov 14, 2018 at 12:04:27PM +0100, Marc Kleine-Budde wrote: >> From: White Ding <bpqw@xxxxxxxxxx> >> >> Do nand reset before write protect check. >> >> If we want to check the WP# low or high through STATUS READ and check bit 7, >> we must reset the device, other operation (eg.erase/program a locked block) can >> also clear the bit 7 of status register. >> >> As we know the status register can be refreshed, if we do some operation to trigger it, >> for example if we do erase/program operation to one block that is locked, then READ STATUS, >> the bit 7 of READ STATUS will be 0 indicate the device in write protect, then if we do >> erase/program operation to another block that is unlocked, the bit 7 of READ STATUS will >> be 1 indicate the device is not write protect. >> Suppose we checked the bit 7 of READ STATUS is 0 then judge the WP# is low (write protect), >> but in this case the WP# maybe high if we do erase/program operation to a locked block, >> so we must reset the device if we want to check the WP# low or high through STATUS READ and >> check bit 7. > > Have you observed a failure this patch fixes or what is your motivation > to send this patch? A $CUSTOMER send me in private a fix needed for the micron NAND chip found his Phytec board or a board they derived from it. I noticed that the fix is in mainline Linux, too and I decided to cherry pick it into barebox. Marc -- Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions | Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
Attachment:
signature.asc
Description: OpenPGP digital signature
_______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
