Re: [PATCH v4 04/11] ARM: allow secure monitor code to be built without PSCI

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Hi Lucas.

On Thu, Nov 01, 2018 at 10:18:39AM +0100, Lucas Stach wrote:
> The hyp mode handling added in the secure monitor code is also useful
> when Barebox doesn't have PSCI control. Allow to build without PSCI.
> 
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> Tested-by: Roland Hieber <r.hieber@xxxxxxxxxxxxxx>
> ---
>  arch/arm/cpu/sm_as.S | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S
> index 09580e75de5f..0d01e1bf2435 100644
> --- a/arch/arm/cpu/sm_as.S
> +++ b/arch/arm/cpu/sm_as.S
> @@ -129,7 +129,9 @@ secure_monitor:
>  	sub	sp, sp, #4*4			@ allocate result structure on stack
>  	mov	r12, sp
>  	push	{r4-r6, r12}
> +#ifdef CONFIG_ARM_PSCI
>  	bl	psci_entry
> +#endif
>  	pop	{r4-r6, r12}
>  	ldm	r12, {r0-r3}
>  	add	sp, sp, #4*4
> @@ -163,6 +165,8 @@ ENTRY(psci_cpu_entry)
>  	mcr	p15, 0, r0, c1, c0, 1	@ ACTLR
>  
>  	bl	secure_monitor_stack_setup
> +#ifdef CONFIG_ARM_PSCI
>  	bl	psci_cpu_entry_c
> +#endif

It looks strange to have two consecutive

	bl  something
	bl  something_else

In the above (when CONFIG_ARM_PSCI is defined).
Seems that we will never hit the second branch long instruction.

But maybe I am just clueless on the assembly syntax?

	Sam

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