PLL3 was first set to 400MHz and then some peripheral was switched
to PLL3. Finally PLL3 was set to 216MHz. This could make some
i.MX538 hang in a dead loop in the boot process.
Signed-off-by: Mogens Lauridsen <mlauridsen171@xxxxxxxxx>
---
arch/arm/mach-imx/imx53.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 56f1bda75..3fdb3b91a 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -119,7 +119,7 @@ void imx53_init_lowlevel_early(unsigned int cpufreq_mhz)
else
imx5_setup_pll_800((void __iomem *)MX53_PLL1_BASE_ADDR);
- imx5_setup_pll_400((void __iomem *)MX53_PLL3_BASE_ADDR);
+ imx5_setup_pll_216((void __iomem *)MX53_PLL3_BASE_ADDR);
/* Switch peripheral to PLL3 */
writel(0x00015154, ccm + MX5_CCM_CBCMR);
@@ -154,7 +154,6 @@ void imx53_init_lowlevel_early(unsigned int cpufreq_mhz)
/* make sure change is effective */
while (readl(ccm + MX5_CCM_CDHIPR));
- imx5_setup_pll_216((void __iomem *)MX53_PLL3_BASE_ADDR);
imx5_setup_pll_455((void __iomem *)MX53_PLL4_BASE_ADDR);
/* Set the platform clock dividers */
--
2.18.0
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