The Advantech ROM-7421 has a custom watchdog reset i2c chip that has
some control gpios. This watchdog is currently not used, therefore mux
its control pins as pull-downs to be sure that the watchdog is disabled
after e.g. a reboot.
For debug purposes this patch also adds i2c1 node.
Signed-off-by: Christoph Fritz <chf.fritz@xxxxxxxxxxxxxx>
---
arch/arm/dts/imx6dl-advantech-rom-7421.dts | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/dts/imx6dl-advantech-rom-7421.dts b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
index 1d5fd89..cdf3781 100755
--- a/arch/arm/dts/imx6dl-advantech-rom-7421.dts
+++ b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
@@ -79,6 +79,13 @@
status = "okay";
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -144,6 +151,17 @@
&iomuxc {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ /* custom watchdog controls disabled */
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x130b0
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
+
+ >;
+ };
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
@@ -175,6 +193,13 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
--
2.1.4
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