There's no point enabling write leveling DQS adjustement, while setting offsets for both slices to zero. This code is effectively a no-op, so drop it. Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx> --- .../include/mach/flash-header/vf610-ddr-cr-default.imxcfg | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg index cce4c6de7..956cc5c58 100644 --- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg +++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg @@ -107,9 +107,6 @@ wm 32 DDRMC_CR88 0x00040000 wm 32 DDRMC_CR89 0x00000002 wm 32 DDRMC_CR91 0x00020000 wm 32 DDRMC_CR96 0x00002819 -wm 32 DDRMC_CR97 0x01000000 -wm 32 DDRMC_CR98 0x00000000 -wm 32 DDRMC_CR99 0x00000000 wm 32 DDRMC_CR102 0x00010100 wm 32 DDRMC_CR105 0x00000000 wm 32 DDRMC_CR106 0x00000004 -- 2.17.0 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
