While creating the previous patch I checked the cpu's reference manual to see what the affected registers actually do and noticed that bits of the DOVE_CPU_CTRL actually used by the code doesn't match the bits described as AHBSlaveBase in the manual. I'm not aware of any effect (neither positive nor negative) of this patch. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> --- arch/arm/mach-mvebu/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c index e951bc06276a..83aeb41ae225 100644 --- a/arch/arm/mach-mvebu/common.c +++ b/arch/arm/mach-mvebu/common.c @@ -219,8 +219,8 @@ void __naked __noreturn dove_barebox_entry(void *boarddata) * The AXI units internal space base starts at the same address as the * DDR controller. */ - val = readl(DOVE_CPU_CTRL) & 0xffff0000; - val |= ((unsigned long)DOVE_SDRAM_BASE & 0xffff0000) >> 16; + val = readl(DOVE_CPU_CTRL) & 0xfff007ff; + val |= ((unsigned long)DOVE_SDRAM_BASE & 0xff800000) >> 12; writel(val, DOVE_CPU_CTRL); barebox_arm_entry(0, dove_memory_find(), boarddata); -- 2.17.0 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
