Re: [PATCH v2 47/48] ARM: i.MX8: Add i.MX8mq EVK support

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On Sat, May 26, 2018 at 01:44:50PM -0700, Andrey Smirnov wrote:
> From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> ---
> +
> +#define reg32_write(a, v)	writel(v, a)
> +#define reg32_read(a)		readl(a)
> +
> +#define DDRC_DDR_SS_GPR0         0x3d000000
> +
> +#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000))
> +#define DDRC_IPS_BASE_ADDR_0	0x3f400000
> +
> +#define DDRC_MSTR_0             0x3d400000
> +#define DDRC_STAT_0             0x3d400004
> +#define DDRC_MSTR1_0            0x3d400008
> +#define DDRC_MRCTRL0_0          0x3d400010

These are all i.MX8M register defines, right? They shouldn't live in the
board support.

> diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c
> new file mode 100644
> index 000000000..81691b2fa
> --- /dev/null
> +void ddr_init(void)
> +{
> +	tmp=reg32_read(0x30360060);
> +	tmp &= ~0x10;
> +	reg32_write(0x30360060,tmp);
> +	do{
> +		tmp=reg32_read(0x30360060);
> +		if(tmp&0x80000000) break;
> +	}while(1);
> +	reg32_write(0x30391000,0x8f000006);
> +	reg32_write(0x3d400304,0x1);
> +	reg32_write(0x3d400030,0x1);

Do we need the defines anyway when the generated code uses raw adresses
and not the defines?

Sascha

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