From: michael grassmann <michael.grassmann@xxxxxxxxx>
The actual RAM timings in the phyFLEX BSP are generated for 528 MHz RAM clock
frequency, but the i.MX 6Solo/DualLite has only a 400 MHz RAM clock. These new
timings are accompanied by a speed increase of approx 10%.
Signed-off-by: michael grassmann <michael.grassmann@xxxxxxxxx>
Signed-off-by: Christian Hemp <c.hemp@xxxxxxxxx>
Signed-off-by: Stefan Riedmueller <s.riedmueller@xxxxxxxxx>
Signed-off-by: Christian Hemp <c.hemp@xxxxxxxxx>
---
.../phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg | 2 +-
.../arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg | 2 +-
arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h | 2 +-
.../phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg | 2 +-
.../phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg | 2 +-
.../phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
index 156eea971e..7b64e5d2fd 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x565c9b85
+ wm 32 0x021b000c 0x41447525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x00000027; \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
index e76867004a..04c489d7e8 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x8c929b85
+ wm 32 0x021b000c 0x2d307525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x00000017; \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
index 405529ddf8..b0f3faa0b7 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
@@ -74,7 +74,7 @@ wm 32 MX6_MMDC_P0_MDOTC 0x09444040
SETUP_MDCFG0
-wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64
+wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8b64
wm 32 MX6_MMDC_P0_MDCFG2 0x01ff0124
wm 32 MX6_MMDC_P0_MDMISC 0x00091740
wm 32 MX6_MMDC_P0_MDSCR 0x00008000
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
index 26fe2b2f7d..ebe5a968b1 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x3c409b85
+ wm 32 0x021b000c 0x2D307525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x0000000B; \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
index babb0dfe24..5f1585a40b 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x3c409b85
+ wm 32 0x021b000c 0x2D307525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x0000000F; \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
index 6a46cd958f..5ff3ec69d7 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
@@ -1,5 +1,5 @@
#define SETUP_MDCFG0 \
- wm 32 0x021b000c 0x565c9b85
+ wm 32 0x021b000c 0x41447525
#define SETUP_MDASP_MDCTL \
wm 32 0x021b0040 0x00000017; \
--
2.16.1
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