The i.MX6 plus SoC variants have some changes in the clock controller, start integrating them beginning with the NAND controller clock. Before doing so we have to add proper detection code for the i.MX6 plus. Sascha Hauer (4): ARM: i.MX6: de-inline i.MX6 type detection ARM: i.MX6: factor out function to read si_rev ARM: i.MX6: Add cpu type for 'plus' variants clk: i.MX6: Fix enfc_sel for i.MX6dqp arch/arm/boards/phytec-som-imx6/board.c | 2 +- arch/arm/boards/zii-imx6q-rdu2/lowlevel.c | 4 +- arch/arm/mach-imx/imx6.c | 42 +++++++++++++--- arch/arm/mach-imx/include/mach/imx6.h | 81 +++++++++++++++++-------------- drivers/clk/imx/clk-imx6.c | 19 +++++++- 5 files changed, 99 insertions(+), 49 deletions(-) -- 2.16.1 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
