On Fri, Sep 29, 2017 at 08:08:28PM +0200, Alexander Kurz wrote: > Hi, > during xchg_single 32 bits will be sent and received: > 2x32 bits / 10 Microseconds = 6.4MHz Clock. why 2x? > Hence, a 10 Microseconds timeout will break SPI communication for > boards with SPI frequencies less then 6.4MHz. > On some boards spi-max-frequency is limited due to improper communication > at higher frequencies, e.g. for the kindle4 it is 1MHz and there > also exists one board with 100kHz. > > Before sending a patch calculating the timeout from spi-max-frequency, > is 640 Microseconds (to fit imx28-cfa10049.dts 100kHz) acceptable? I would expect that the hardware and software add some latency, so maybe round it up to 1 ms? Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ | _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
