Am Mittwoch, den 27.09.2017, 14:16 +0200 schrieb Sascha Hauer:
> On i.MX6ull (Cortex A7) We have to set the SMP bit before enabling
> the
> caches, otherwise they won't work. Add a SoC specific lowlevel_init
> function to be called by the i.MX6ull boards.
This isn't specific to the MX6ULL, but the Cortex-A7, which is used in
the whole MX6UL family. So I would prefer if this is called imx6ul_...
Also a follow-up commit should switch over the already supported
MX6UL/ULL boards to the new init function.
Regards,
Lucas
> Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> ---
> arch/arm/mach-imx/cpu_init.c | 12 ++++++++++++
> arch/arm/mach-imx/include/mach/generic.h | 1 +
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-
> imx/cpu_init.c
> index 2b388cad8c..8f6d4b7902 100644
> --- a/arch/arm/mach-imx/cpu_init.c
> +++ b/arch/arm/mach-imx/cpu_init.c
> @@ -14,6 +14,7 @@
>
> #include <asm/barebox-arm-head.h>
> #include <asm/errata.h>
> +#include <linux/types.h>
>
> void imx5_cpu_lowlevel_init(void)
> {
> @@ -34,6 +35,17 @@ void imx6_cpu_lowlevel_init(void)
> enable_arm_errata_845369_war();
> }
>
> +void imx6ull_cpu_lowlevel_init(void)
> +{
> + u32 val;
> +
> + asm volatile ("mrc p15, 0, %0, c1, c0, 1\n" : "=r"(val));
> + val |= (1 << 6);
> + asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (val));
> +
> + arm_cpu_lowlevel_init();
> +}
> +
> void imx7_cpu_lowlevel_init(void)
> {
> arm_cpu_lowlevel_init();
> diff --git a/arch/arm/mach-imx/include/mach/generic.h
> b/arch/arm/mach-imx/include/mach/generic.h
> index 73be9ceb55..eb8c7a5b7b 100644
> --- a/arch/arm/mach-imx/include/mach/generic.h
> +++ b/arch/arm/mach-imx/include/mach/generic.h
> @@ -48,6 +48,7 @@ int imx6_devices_init(void);
>
> void imx5_cpu_lowlevel_init(void);
> void imx6_cpu_lowlevel_init(void);
> +void imx6ull_cpu_lowlevel_init(void);
> void imx7_cpu_lowlevel_init(void);
> void vf610_cpu_lowlevel_init(void);
>
_______________________________________________
barebox mailing list
barebox@xxxxxxxxxxxxxxxxxxx
http://lists.infradead.org/mailman/listinfo/barebox
