2017-07-28 15:42 GMT+02:00 Andrey Smirnov <andrew.smirnov@xxxxxxxxx>: > On Fri, Jul 28, 2017 at 6:24 AM, Mabcded Babcde > <thepusherpushes@xxxxxxxxx> wrote: >> 2017-07-27 20:49 GMT+02:00 Andrey Smirnov <andrew.smirnov@xxxxxxxxx>: >>> On Thu, Jul 27, 2017 at 9:20 AM, Mabcded Babcde >>> <thepusherpushes@xxxxxxxxx> wrote: >>>> Hi, >>>> this patch adds a new command to barebox. It is used to enable or >>>> disable the fpga-to-sdram bridges on socfpgas. The patch is based on a >>>> manual from altera >>>> (https://www.altera.com/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html) >>>> and a implementation for u-boot >>>> (https://github.com/rogerq/u-boot/blob/master/arch/arm/mach-socfpga/misc.c). >>>> The fpga2sdram fpga configuration can only be set when the SDRAM >>>> interface is idle. So it is necessary to use the on-chip ram. >>> >>> And by "on-chip ram" you mean i-cache and not SRAM block used by first >>> stage bootloader, correct? I am just a bit confused by the wording. >>> >> >> Sorry, my fault. I meant i-cache. >> >>>> To bring all fpga2sdram bridges out of reset it is necessary to write 0x3FFF to >>>> the register. Only the fpga2sdram bridges are enabled or disabled but >>>> no other bridges like the axi bridges. >>> >>> Linux kernel already has: >>> >>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt?h=v4.13-rc2 >>> >>> so, IMHO, it would be better to implement a compatible driver and, if >>> ability to change the value at run-time is needed, add "enable" >>> property to it rather than introducing a separate command. >>> >> >> But how can I ensure that the SDRAM is idle? I quote Altera: >> "First time enabling of the FPGA2SDRAM bridge within Linux is not >> supported as the SDRAM subsystem cannot be easily put into a >> guaranteed idle state." >> > > I feel like we are talking about different things. What I am trying to > say that instead of adding this functionality to Barebox as a > standalone command, it would be better to add it _to Barebox_ as a > driver that claims compatibility with "altr,socfpga-fpga2sdram-bridge" > and implements all of the necessary logic there. It would be the same > code running in the boot-loader but triggered to executed via > different means, so it should literally be the same in terms of SDRAM > access quiescence. A somewhat relative example of that approach would > be "drivers/firmware/socfpga.c". Ok, I hardcoded my code from the command to drivers/firmware/socfpga.c for testing purposes. That didn't seem to work. However how would I enable or disable the bridge? With a parameter? Where can I add it and change it? > >> >>>> I'm a beginner to embedded and >>>> open-source software. This is the reason why I don't know to which >>>> branch I have to push this patch and I don't know which license should >>>> be applied here because I used some code from another source (see >>>> above GPL License / Altera). Nevertheless I would be happy to >>>> contribute to Barebox. >>>> Thanks, Mathieu >>>> >>>> >>>> --- >>> >>> Just in case you didn't know this already, text below this line will >>> be ignored when the patch is applied, so this is a great place to put >>> some technical or personal notes that might not necessarily belong to >>> the commit message. >>> >> >> Thanks! >> >>> >>>> commands/Kconfig | 7 ++++ >>>> commands/Makefile | 1 + >>>> commands/f2sbridge.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++++ >>>> 3 files changed, 100 insertions(+) >>>> create mode 100644 commands/f2sbridge.c >>>> >>>> diff --git a/commands/Kconfig b/commands/Kconfig >>>> index ae2dc4b..328ab1b 100644 >>>> --- a/commands/Kconfig >>>> +++ b/commands/Kconfig >>>> @@ -2127,6 +2127,13 @@ config CMD_SEED >>>> help >>>> Seed the pseudo random number generator (PRNG) >>>> >>>> +config CMD_F2SBRIDGE >>>> + bool >>>> + depends on ARCH_SOCFPGA >>>> + prompt "f2sbridge" >>>> + help >>>> + Enables or disables the fpga2sdram bridge >>>> + >>>> # end Miscellaneous commands >>>> endmenu >>>> >>>> diff --git a/commands/Makefile b/commands/Makefile >>>> index 37486dc..2006bca 100644 >>>> --- a/commands/Makefile >>>> +++ b/commands/Makefile >>>> @@ -123,3 +123,4 @@ obj-$(CONFIG_CMD_SPD_DECODE) += spd_decode.o >>>> obj-$(CONFIG_CMD_MMC_EXTCSD) += mmc_extcsd.o >>>> obj-$(CONFIG_CMD_NAND_BITFLIP) += nand-bitflip.o >>>> obj-$(CONFIG_CMD_SEED) += seed.o >>>> +obj-$(CONFIG_CMD_F2SBRIDGE) += f2sbridge.o >>>> diff --git a/commands/f2sbridge.c b/commands/f2sbridge.c >>>> new file mode 100644 >>>> index 0000000..8d3bbcc >>>> --- /dev/null >>>> +++ b/commands/f2sbridge.c >>>> @@ -0,0 +1,92 @@ >>>> +/* >>>> + * Copyright (C) ??? >>> >>> Maybe: >>> >>> Copyright (C) 2017 Your Name >>> >>> Based on the code form U-Boot >>> >>> Copyright (C) Year, Altera >>> >>> ? >> >> Thanks! >> >>> >>>> + * >>>> + * SPDX-License-Identifier: GPL-2.0+ >>>> + */ >>>> + >>>> + >>>> +#include <common.h> >>>> +#include <io.h> >>>> +#include <command.h> >>>> + >>>> +#define SOCFPGA_SYSMGR_ADDRESS 0xFFD08000 >>>> +#define SOCFPGA_SDR_ADDRESS 0xFFC20000 >>>> + >>>> +#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 >>>> +#define SDR_CTRLGRP_STATICCFG_ADDRESS 0x505C >>>> +#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 >>>> + >>>> +#define SYSMGR_FPGAINTF_MODULE (SOCFPGA_SYSMGR_ADDRESS + 0x28) >>>> + >>>> + >>>> +static void socfpga_sdram_apply_staticcfg(void) >>>> +{ >>>> + const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + >>>> SDR_CTRLGRP_STATICCFG_ADDRESS; >>>> + const uint32_t applymask = SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK; >>>> + uint32_t val = readl(staticcfg) | applymask; >>>> + >>>> + /* >>>> + * SDRAM staticcfg register specific: >>>> + * When applying the register setting, the CPU must not access >>>> + * SDRAM. Luckily for us, we can abuse i-cache here to help us >>>> + * circumvent the SDRAM access issue. The idea is to make sure >>>> + * that the code is in one full i-cache line by branching past >>>> + * it and back. Once it is in the i-cache, we execute the core >>>> + * of the code and apply the register settings. >>>> + * >>>> + * The code below uses 7 instructions, while the Cortex-A9 has >>>> + * 32-byte cachelines, thus the limit is 8 instructions total. >>>> + */ >>>> + asm volatile( >>>> + ".align 5 \n" >>>> + " b 2f \n" >>>> + "1: str %0, [%1] \n" >>>> + " dsb \n" >>>> + " isb \n" >>>> + " b 3f \n" >>>> + "2: b 1b \n" >>>> + "3: nop \n" >>>> + : : "r"(val), "r"(staticcfg) : "memory", "cc"); >>>> +} >>>> + >>>> + >>>> +int do_f2sbridge(int argc, char *argv[]) >>>> +{ >>>> + if (argc != 2) >>>> + return COMMAND_ERROR_USAGE; >>>> + >>>> + switch (*argv[1]) { >>>> + case 'e': // Enable >>>> + // hps peripheral controller to fpga >>>> + iowrite32(0, SYSMGR_FPGAINTF_MODULE); >>> >>> You use readl() above but iowrite32() (as opposed to writel()) here, >>> is that on purpose? >> >> That was a mistake. I changed it to ioread32. >> > > I'd maybe convert it the other around since there are very few users > of "ioread32" in the codebase and readl()/writel() seem to be more > idiomatic. Ok, but I thought readl()/writel() are less safe? > > Thanks, > Andrey Smirnov Thanks, Mathieu _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
