The size field in the window control register occupies bits 31:16. So adapt ARMADA_370_XP_DDR_SIZE_MASK accordingly. This fixes detection of RAM chips smaller than 32 MiB and so probably doesn't affect any supported machine. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> --- arch/arm/mach-mvebu/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c index 06bfb7261544..fa971da11e75 100644 --- a/arch/arm/mach-mvebu/common.c +++ b/arch/arm/mach-mvebu/common.c @@ -47,7 +47,7 @@ #define ARMADA_370_XP_SDRAM_BASE (IOMEM(MVEBU_REMAP_INT_REG_BASE) + 0x20000) #define ARMADA_370_XP_DDR_SIZE_CSn(n) (0x184 + ((n) * 0x8)) #define ARMADA_370_XP_DDR_SIZE_ENABLED BIT(0) -#define ARMADA_370_XP_DDR_SIZE_MASK 0xff000000 +#define ARMADA_370_XP_DDR_SIZE_MASK 0xffff0000 /* * Marvell MVEBU SoC id and revision can be read from any PCIe -- 2.11.0 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
