The CPU write buffer needs to be coherent with the cache, otherwise we might flush stale entries with the actual data stuck in the cache. This is really important on newer CPU core with bigger write buffers. Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> --- arch/arm/cpu/cache-armv7.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index c19618bde182..aaa8bf8c62e1 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -68,6 +68,7 @@ ENTRY(v7_mmu_cache_flush) ENDPROC(v7_mmu_cache_flush) ENTRY(__v7_mmu_cache_flush_invalidate) + mcr p15, 0, r12, c7, c10, 5 @ DMB mrc p15, 0, r12, c0, c1, 5 @ read ID_MMFR1 tst r12, #0xf << 16 @ hierarchical cache (ARMv7) mov r12, #0 -- 2.11.0 _______________________________________________ barebox mailing list barebox@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/barebox
