This is necessary to make second stage booting work when the register
window is already moved.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>
---
arch/arm/boards/netgear-rn2120/lowlevel.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boards/netgear-rn2120/lowlevel.c b/arch/arm/boards/netgear-rn2120/lowlevel.c
index 5cde2b657bd5..59b9985ca9d8 100644
--- a/arch/arm/boards/netgear-rn2120/lowlevel.c
+++ b/arch/arm/boards/netgear-rn2120/lowlevel.c
@@ -16,12 +16,14 @@
#include <asm/barebox-arm-head.h>
#include <asm/io.h>
#include <mach/lowlevel.h>
+#include <mach/common.h>
extern char __dtb_armada_xp_rn2120_bb_start[];
ENTRY_FUNCTION(start_netgear_rn2120, r0, r1, r2)
{
void *fdt;
+ void __iomem *base = mvebu_get_initial_int_reg_base();
arm_cpu_lowlevel_init();
@@ -31,8 +33,8 @@ ENTRY_FUNCTION(start_netgear_rn2120, r0, r1, r2)
* SoC reset.
* This is effectively gpio_direction_output(42, 1);
*/
- writel((1 << 10) | readl((void *)0xd0018140), (void *)0xd0018140);
- writel(~(1 << 10) & readl((void *)0xd0018144), (void *)0xd0018144);
+ writel((1 << 10) | readl(base + 0x18140), base + 0x18140);
+ writel(~(1 << 10) & readl(base + 0x18144), base + 0x18144);
/*
* The vendor binary that initializes RAM doesn't program the SDRAM
@@ -41,13 +43,13 @@ ENTRY_FUNCTION(start_netgear_rn2120, r0, r1, r2)
*/
/* Win 1 Base Address Register: base=0x40000000 */
- writel(0x40000000, (void *)0xd0020188);
+ writel(0x40000000, base + 0x20188);
/* Win 1 Control Register: size=0x4000000, wincs=1, en=1*/
- writel(0x3fffffe5, (void *)0xd002018c);
+ writel(0x3fffffe5, base + 0x2018c);
/* Win 0 Base Address Register is already 0, base=0x00000000 */
/* Win 0 Control Register: size=0x4000000, wincs=0, en=1 */
- writel(0x3fffffe1, (void *)0xd0020184);
+ writel(0x3fffffe1, base + 0x20184);
fdt = __dtb_armada_xp_rn2120_bb_start -
get_runtime_offset();
--
2.11.0
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