Hi Uwe,
On Fri, Feb 10, 2017 at 04:50:59PM +0100, Uwe Kleine-König wrote:
> While assuming SZ_64M initially is save and fixed up later, the size of the
> malloc area is determined from this value. So it might make sense for some
> boards to pass the correct version from the start to have more RAM available
> for example to write big images into an FPGA.
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>
> ---
> arch/arm/boards/globalscale-guruplug/lowlevel.c | 2 +-
> arch/arm/boards/globalscale-mirabox/lowlevel.c | 2 +-
> arch/arm/boards/lenovo-ix4-300d/lowlevel.c | 2 +-
> arch/arm/boards/marvell-armada-xp-gp/lowlevel.c | 2 +-
> arch/arm/boards/netgear-rn104/lowlevel.c | 2 +-
> arch/arm/boards/netgear-rn2120/lowlevel.c | 2 +-
> arch/arm/boards/plathome-openblocks-a6/lowlevel.c | 2 +-
> arch/arm/boards/plathome-openblocks-ax3/lowlevel.c | 2 +-
> arch/arm/boards/solidrun-cubox/lowlevel.c | 2 +-
> arch/arm/boards/usi-topkick/lowlevel.c | 2 +-
> arch/arm/mach-mvebu/include/mach/lowlevel.h | 2 +-
> arch/arm/mach-mvebu/lowlevel.c | 15 +++++++--------
> 12 files changed, 18 insertions(+), 19 deletions(-)
>
> /*
> * Determining the actual memory size is highly SoC dependent,
> - * but for all SoCs RAM starts at 0x00000000. Therefore, we start
> - * with a minimal memory setup of 64M and probe correct memory size
> - * later.
> + * but for all SoCs RAM starts at 0x00000000. If the available RAM isn't known
> + * at the call-site of mvebu_barebox_entry, using a value that is not too big is
> + * safe. The correct memory size will be probed later.
> */
> #define MVEBU_BOOTUP_MEMORY_BASE 0x00000000
> -#define MVEBU_BOOTUP_MEMORY_SIZE SZ_64M
>
> -void __naked __noreturn mvebu_barebox_entry(void *boarddata)
> +void __naked __noreturn mvebu_barebox_entry(void *boarddata,
> + unsigned long memsize)
> {
> mvebu_remap_registers();
> - barebox_arm_entry(MVEBU_BOOTUP_MEMORY_BASE,
> - MVEBU_BOOTUP_MEMORY_SIZE, boarddata);
> + barebox_arm_entry(MVEBU_BOOTUP_MEMORY_BASE, memsize, boarddata);
> }
I would prefer if you could split mvebu_barebox_entry into
armada_370_xp_barebox_entry, dove_barebox_entry and
kirkwood_barebox_entry. Then you could call the SoC specific SDRAM
detection functions and call barebox with the correct amount of SDRAM
from the start.
Sascha
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